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rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3

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Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various
GMAC related fields.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Sjoerd Simons 2016-02-28 22:25:00 +01:00 committed by Simon Glass
parent 0aefc0b0c7
commit 2f3920047a
1 changed files with 53 additions and 0 deletions
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53
arch/arm/include/asm/arch-rockchip/grf_rk3288.h
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@ -718,6 +718,40 @@ enum {
MSCH0_MAINPARTIALPOP_MASK = 1,
};
/* GRF_SOC_CON1 */
enum {
RMII_MODE_SHIFT = 0xe,
RMII_MODE_MASK = 1,
RMII_MODE = 1,
GMAC_CLK_SEL_SHIFT = 0xc,
GMAC_CLK_SEL_MASK = 3,
GMAC_CLK_SEL_125M = 0,
GMAC_CLK_SEL_25M = 0x3,
GMAC_CLK_SEL_2_5M = 0x2,
RMII_CLK_SEL_SHIFT = 0xb,
RMII_CLK_SEL_MASK = 1,
RMII_CLK_SEL_2_5M = 0,
RMII_CLK_SEL_25M,
GMAC_SPEED_SHIFT = 0xa,
GMAC_SPEED_MASK = 1,
GMAC_SPEED_10M = 0,
GMAC_SPEED_100M,
GMAC_FLOWCTRL_SHIFT = 0x9,
GMAC_FLOWCTRL_MASK = 1,
GMAC_PHY_INTF_SEL_SHIFT = 0x6,
GMAC_PHY_INTF_SEL_MASK = 0x7,
GMAC_PHY_INTF_SEL_RGMII = 0x1,
GMAC_PHY_INTF_SEL_RMII = 0x4,
HOST_REMAP_SHIFT = 0x5,
HOST_REMAP_MASK = 1
};
/* GRF_SOC_CON2 */
enum {
UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
@ -765,4 +799,23 @@ enum {
PWM_PWM = 0,
};
/* GRF_SOC_CON3 */
enum {
RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
RXCLK_DLY_ENA_GMAC_MASK = 1,
RXCLK_DLY_ENA_GMAC_DISABLE = 0,
RXCLK_DLY_ENA_GMAC_ENABLE,
TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
TXCLK_DLY_ENA_GMAC_MASK = 1,
TXCLK_DLY_ENA_GMAC_DISABLE = 0,
TXCLK_DLY_ENA_GMAC_ENABLE,
CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
CLK_RX_DL_CFG_GMAC_MASK = 0x7f,
CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
CLK_TX_DL_CFG_GMAC_MASK = 0x7f,
};
#endif