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Patches by Kshitij, 04 Jul 2003

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- added support for arm925t cpu core
- added support for TI OMAP 1510 Innovator Board
This commit is contained in:
wdenk
2003-07-15 20:04:06 +00:00
parent 6dff552972
commit 2e5983d2ea
25 changed files with 3088 additions and 14 deletions
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47
board/omap1510inn/Makefile Normal file
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#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := omap1510innovator.o flash.o
SOBJS := platform.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

25
board/omap1510inn/config.mk Normal file
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#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2003
# Texas Instruments, <www.ti.com>
# Kshitij Gupta <Kshitij@ti.com>
#
# TI Innovator board with OMAP1510 (ARM925T) cpu
# see http://www.ti.com/ for more information on Texas Insturments
#
# Innovator has 1 bank of 256 MB SDRAM
# Physical Address:
# 1000'0000 to 2000'0000
#
#
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
#
# we load ourself to 1100'0000
#
#
TEXT_BASE = 0x11000000

428
board/omap1510inn/flash.c Normal file
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/*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/byteorder/swab.h>
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect ( FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
volatile FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
mb ();
value = addr[0];
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
switch (value) {
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/*start = get_timer (0); */
last = start;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = (FPW) 0x00500050; /* clear status register cmd. */
*addr = (FPW) 0x00FF00FF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, SWAP (data)));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

131
board/omap1510inn/omap1510innovator.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
static void flash__init (void);
static void ether__init (void);
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* arch number of OMAP 1510-Board */
gd->bd->bi_arch_number = 234;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
/* kk - this speeds up your boot a quite a bit. However to make it
* work, you need make sure your kernel startup flush bug is fixed.
* ... rkw ...
*/
icache_enable ();
flash__init ();
ether__init ();
return 0;
}
int misc_init_r (void)
{
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
/* setup gpio direction to match board (no floats!) */
/**gdir = 0xCFF9; */
/**mdir = 0x103F; */
return (0);
}
/******************************
Routine:
Description:
******************************/
static void flash__init (void)
{
#define CS0_CHIP_SELECT_REG 0xfffecc10
#define CS3_CHIP_SELECT_REG 0xfffecc1c
#define EMIFS_GlB_Config_REG 0xfffecc0c
{
unsigned int regval;
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
regval = regval | 0x0001; /* Turn off write protection for flash devices. */
if (regval & 0x0002) {
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
}
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
}
}
/******************************
Routine:
Description:
******************************/
static void ether__init (void)
{
#define ETH_CONTROL_REG 0x0800000b
/* take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
*/
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
udelay (3);
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}

386
board/omap1510inn/platform.S Normal file
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/*
* Board specific setup info
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
*
* -- Some bits of code used from rrload's head_OMAP1510.s --
* Copyright (C) 2002 RidgeRun, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#if defined(CONFIG_OMAP1510)
#include <./configs/omap1510.h>
#endif
#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
.globl platformsetup
platformsetup:
/*
* Configure 1510 pins functions to match our board.
*/
ldr r0, REG_PULL_DWN_CTRL_0
ldr r1, VAL_PULL_DWN_CTRL_0
str r1, [r0]
ldr r0, REG_PULL_DWN_CTRL_1
ldr r1, VAL_PULL_DWN_CTRL_1
str r1, [r0]
ldr r0, REG_PULL_DWN_CTRL_2
ldr r1, VAL_PULL_DWN_CTRL_2
str r1, [r0]
ldr r0, REG_PULL_DWN_CTRL_3
ldr r1, VAL_PULL_DWN_CTRL_3
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_4
ldr r1, VAL_FUNC_MUX_CTRL_4
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_5
ldr r1, VAL_FUNC_MUX_CTRL_5
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_6
ldr r1, VAL_FUNC_MUX_CTRL_6
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_7
ldr r1, VAL_FUNC_MUX_CTRL_7
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_8
ldr r1, VAL_FUNC_MUX_CTRL_8
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_9
ldr r1, VAL_FUNC_MUX_CTRL_9
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_A
ldr r1, VAL_FUNC_MUX_CTRL_A
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_B
ldr r1, VAL_FUNC_MUX_CTRL_B
str r1, [r0]
ldr r0, REG_FUNC_MUX_CTRL_C
ldr r1, VAL_FUNC_MUX_CTRL_C
str r1, [r0]
ldr r0, REG_VOLTAGE_CTRL_0
ldr r1, VAL_VOLTAGE_CTRL_0
str r1, [r0]
ldr r0, REG_TEST_DBG_CTRL_0
ldr r1, VAL_TEST_DBG_CTRL_0
str r1, [r0]
ldr r0, REG_MOD_CONF_CTRL_0
ldr r1, VAL_MOD_CONF_CTRL_0
str r1, [r0]
/* Move to 1510 mode */
ldr r0, REG_COMP_MODE_CTRL_0
ldr r1, VAL_COMP_MODE_CTRL_0
str r1, [r0]
/* Set up Traffic Ctlr*/
ldr r0, REG_TC_IMIF_PRIO
mov r1, #0x0
str r1, [r0]
ldr r0, REG_TC_EMIFS_PRIO
str r1, [r0]
ldr r0, REG_TC_EMIFF_PRIO
str r1, [r0]
ldr r0, REG_TC_EMIFS_CONFIG
ldr r1, [r0]
bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
/* Setup some clock domains */
ldr r1, =OMAP1510_CLKS
ldr r0, REG_ARM_IDLECT2
strh r1, [r0] /* CLKM, Clock domain control. */
mov r1, #0x01 /* PER_EN bit */
ldr r0, REG_ARM_RSTCT2
strh r1, [r0] /* CLKM; Peripheral reset. */
/* Set CLKM to Sync-Scalable */
/* I supposidly need to enable the dsp clock before switching */
mov r1, #0x1000
ldr r0, REG_ARM_SYSST
strh r1, [r0]
mov r0, #0x400
1:
subs r0, r0, #0x1 /* wait for any bubbles to finish */
bne 1b
ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
ldr r0, REG_ARM_CKCTL
strh r1, [r0]
/* setup DPLL 1 */
ldr r1, VAL_DPLL1_CTL
ldr r0, REG_DPLL1_CTL
strh r1, [r0]
ands r1, r1, #0x10 /* Check if PLL is enabled. */
beq lock_end /* Do not look for lock if BYPASS selected */
2:
ldrh r1, [r0]
ands r1, r1, #0x01 /* Check the LOCK bit. */
beq 2b /* ...loop until bit goes hi. */
lock_end:
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location
* and branch to appropriate initialization code.
*/
mov r0, #0x10000000 /* Load physical SDRAM base. */
mov r1, pc /* Get current execution location. */
cmp r1, r0 /* Compare. */
bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
/*
* Delay for SDRAM initialization.
*/
mov r3, #0x1800 /* value should be checked */
3:
subs r3, r3, #0x1 /* Decrement count */
bne 3b
/*
* Set SDRAM control values. Disable refresh before MRS command.
*/
ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
str r3, [r2] /* Store the passed value with AR disabled. */
ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
str r1, [r2] /* Store the passed value.*/
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
str r0, [r2] /* Store the passed value. */
/*
* Delay for SDRAM initialization.
*/
mov r3, #0x1800
4:
subs r3, r3, #1 /* Decrement count. */
bne 4b
skip_sdram:
/* slow interface */
ldr r1, VAL_TC_EMIFS_CS0_CONFIG
ldr r0, REG_TC_EMIFS_CS0_CONFIG
str r1, [r0] /* Chip Select 0 */
ldr r1, VAL_TC_EMIFS_CS1_CONFIG
ldr r0, REG_TC_EMIFS_CS1_CONFIG
str r1, [r0] /* Chip Select 1 */
ldr r1, VAL_TC_EMIFS_CS2_CONFIG
ldr r0, REG_TC_EMIFS_CS2_CONFIG
str r1, [r0] /* Chip Select 2 */
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] /* Chip Select 3 */
/* Next, Enable the RS232 Line Drivers in the FPGA. */
/* Also, power on the audio CODEC's amplifier here, */
/* which will make a noise on the audio output. */
/* This is done here instead of in the kernel so there */
/* isn't a loud popping noise at the start of each */
/* song. */
/* Also, disable the CODEC's clocks. */
/* omap1510-HelenP1 [specific] */
ldr r0, REG_FPGA_POWER
mov r1, #0
ldr r2, REG_FPGA_DIP_SWITCH
ldrb r3, [r2]
cmp r3, #0x8
movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */
strb r1, [r0]
ldr r0, REG_FPGA_AUDIO
mov r1, #0x0 /* Disable sound driver (CODEC clocks) */
strb r1, [r0]
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
/* OMAP configuration registers */
REG_FUNC_MUX_CTRL_0: /* 32 bits */
.word 0xfffe1000
REG_FUNC_MUX_CTRL_1: /* 32 bits */
.word 0xfffe1004
REG_FUNC_MUX_CTRL_2: /* 32 bits */
.word 0xfffe1008
REG_COMP_MODE_CTRL_0: /* 32 bits */
.word 0xfffe100c
REG_FUNC_MUX_CTRL_3: /* 32 bits */
.word 0xfffe1010
REG_FUNC_MUX_CTRL_4: /* 32 bits */
.word 0xfffe1014
REG_FUNC_MUX_CTRL_5: /* 32 bits */
.word 0xfffe1018
REG_FUNC_MUX_CTRL_6: /* 32 bits */
.word 0xfffe101c
REG_FUNC_MUX_CTRL_7: /* 32 bits */
.word 0xfffe1020
REG_FUNC_MUX_CTRL_8: /* 32 bits */
.word 0xfffe1024
REG_FUNC_MUX_CTRL_9: /* 32 bits */
.word 0xfffe1028
REG_FUNC_MUX_CTRL_A: /* 32 bits */
.word 0xfffe102C
REG_FUNC_MUX_CTRL_B: /* 32 bits */
.word 0xfffe1030
REG_FUNC_MUX_CTRL_C: /* 32 bits */
.word 0xfffe1034
REG_FUNC_MUX_CTRL_D: /* 32 bits */
.word 0xfffe1038
REG_PULL_DWN_CTRL_0: /* 32 bits */
.word 0xfffe1040
REG_PULL_DWN_CTRL_1: /* 32 bits */
.word 0xfffe1044
REG_PULL_DWN_CTRL_2: /* 32 bits */
.word 0xfffe1048
REG_PULL_DWN_CTRL_3: /* 32 bits */
.word 0xfffe104c
REG_VOLTAGE_CTRL_0: /* 32 bits */
.word 0xfffe1060
REG_TEST_DBG_CTRL_0: /* 32 bits */
.word 0xfffe1070
REG_MOD_CONF_CTRL_0: /* 32 bits */
.word 0xfffe1080
REG_TC_IMIF_PRIO: /* 32 bits */
.word 0xfffecc00
REG_TC_EMIFS_PRIO: /* 32 bits */
.word 0xfffecc04
REG_TC_EMIFF_PRIO: /* 32 bits */
.word 0xfffecc08
REG_TC_EMIFS_CONFIG: /* 32 bits */
.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
.word 0xfffecc1c
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
.word 0xfffecc20
REG_TC_EMIFF_MRS: /* 32 bits */
.word 0xfffecc24
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL: /* 16 bits */
.word 0xfffece00
REG_ARM_IDLECT2: /* 16 bits */
.word 0xfffece08
REG_ARM_RSTCT2: /* 16 bits */
.word 0xfffece14
REG_ARM_SYSST: /* 16 bits */
.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL: /* 16 bits */
.word 0xfffecf00
/* identification code register */
REG_IDCODE: /* 32 bits */
.word 0xfffed404
/* Innovator specific */
REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
.word 0x08000003
REG_FPGA_POWER: /* 8 bits */
.word 0x08000005
REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
.word 0x0800000c
REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
.word 0x0800000e
VAL_COMP_MODE_CTRL_0:
.word 0x0000eaef
VAL_FUNC_MUX_CTRL_4:
.word 0x00000000
VAL_FUNC_MUX_CTRL_5:
.word 0x00000000
VAL_FUNC_MUX_CTRL_6:
.word 0x00000001
VAL_FUNC_MUX_CTRL_7:
.word 0x00000000
VAL_FUNC_MUX_CTRL_8:
.word 0x10001200
VAL_FUNC_MUX_CTRL_9:
.word 0x01201012
VAL_FUNC_MUX_CTRL_A:
.word 0x00000248
VAL_FUNC_MUX_CTRL_B:
.word 0x00000248
VAL_FUNC_MUX_CTRL_C:
.word 0x09000000
VAL_FUNC_MUX_CTRL_D:
.word 0x00000000
VAL_PULL_DWN_CTRL_0:
.word 0x11a10000
VAL_PULL_DWN_CTRL_1:
.word 0x2e047fff
VAL_PULL_DWN_CTRL_2:
.word 0xffd7d3e6
VAL_PULL_DWN_CTRL_3:
.word 0x00003f03
VAL_VOLTAGE_CTRL_0:
.word 0x00000007
VAL_TEST_DBG_CTRL_0:
/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
* This slows down internal SRAM accesses.
*/
.word 0x00000007
VAL_MOD_CONF_CTRL_0:
.word 0x0b000008
VAL_ARM_CKCTL:
.word 0x010f
VAL_DPLL1_CTL:
.word 0x2710
VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
.word 0x00001149
VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
.word 0x00004158
VAL_TC_EMIFS_CS0_CONFIG:
.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
.word 0x0000f559
VAL_TC_EMIFS_CS2_CONFIG:
.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
.word 0x00003331
VAL_TC_EMIFF_SDRAM_CONFIG:
.word 0x010290fc
VAL_TC_EMIFF_MRS:
.word 0x00000027

58
board/omap1510inn/u-boot.lds Normal file
View File

@@ -0,0 +1,58 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm925t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
armboot_end_data = .;
. = ALIGN(4);
.bss : { *(.bss) }
armboot_end = .;
}