* Patches by Martin Krause, 14 Jul 2003:
- add I2C support for s3c2400 systems (trab board) - (re-) add "ping" to command table * Fix handling of "slow" POST routines
This commit is contained in:
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@ -2,6 +2,12 @@
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Changes for U-Boot 0.4.3:
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======================================================================
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* Patches by Martin Krause, 14 Jul 2003:
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- add I2C support for s3c2400 systems (trab board)
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- (re-) add "ping" to command table
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* Fix handling of "slow" POST routines
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* Patches by Yuli Barcohen, 13 Jul 2003:
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- Correct flash and JFFS2 support for MPC8260ADS
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- fix PVR values and clock generation for PowerQUICC II family
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5
README
5
README
@ -3048,6 +3048,11 @@ it:
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version of diff does not support these options, then get the latest
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version of GNU diff.
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The current directory when running this command shall be the top
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level directory of the U-Boot source tree, or it's parent directory
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(i. e. please make sure that your patch includes sufficient
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directory information for the affected files).
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We accept patches as plain text, MIME attachments or as uuencoded
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gzipped text.
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@ -1087,7 +1087,6 @@ int post_hotkeys_pressed(gd_t *gd)
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i2c_write (kbd_addr, 0, 0, &val, 1);
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i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
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return (gd->post_hotkeys_latch =
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(compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
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return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
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}
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#endif
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@ -130,6 +130,11 @@ int board_init ()
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}
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#endif /* CONFIG_MODEM_SUPPORT */
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#ifdef CONFIG_DRIVER_S3C24X0_I2C
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/* Configure I/O ports PG5 und PG6 for I2C */
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gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
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#endif /* CONFIG_DRIVER_S3C24X0_I2C */
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return 0;
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}
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@ -210,6 +210,12 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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return 0;
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}
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U_BOOT_CMD(
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ping, 2, 1, do_ping,
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"ping - send ICMP ECHO_REQUEST to network host\n",
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"pingAddress\n"
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);
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#endif /* CFG_CMD_PING */
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#endif /* CFG_CMD_NET */
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@ -63,7 +63,12 @@ static int GetI2CSDA(void)
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{
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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#ifdef CONFIG_S3C2410
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return (gpio->GPEDAT & 0x8000) >> 15;
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#endif
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#ifdef CONFIG_S3C2400
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return (gpio->PGDAT & 0x0020) >> 5;
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#endif
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}
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#if 0
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@ -77,7 +82,12 @@ static void SetI2CSCL(int x)
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{
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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#ifdef CONFIG_S3C2410
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gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
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#endif
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#ifdef CONFIG_S3C2400
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gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
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#endif
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}
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@ -129,11 +139,22 @@ void i2c_init (int speed, int slaveadd)
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}
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if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
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#ifdef CONFIG_S3C2410
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ulong old_gpecon = gpio->GPECON;
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#endif
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#ifdef CONFIG_S3C2400
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ulong old_gpecon = gpio->PGCON;
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#endif
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/* bus still busy probably by (most) previously interrupted transfer */
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#ifdef CONFIG_S3C2410
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/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
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gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
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#endif
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#ifdef CONFIG_S3C2400
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/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
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gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
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#endif
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/* toggle I2CSCL until bus idle */
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SetI2CSCL(0); udelay(1000);
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@ -146,7 +167,12 @@ void i2c_init (int speed, int slaveadd)
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SetI2CSCL(1); udelay(1000);
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/* restore pin functions */
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#ifdef CONFIG_S3C2410
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gpio->GPECON = old_gpecon;
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#endif
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#ifdef CONFIG_S3C2400
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gpio->PGCON = old_gpecon;
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#endif
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}
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/* calculate prescaler and divisor values */
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@ -73,7 +73,6 @@ typedef struct global_data {
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#ifdef CONFIG_POST
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unsigned long post_log_word; /* Record POST activities */
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unsigned long post_init_f_time; /* When post_init_f started */
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unsigned long post_hotkeys_latch; /* If the post hotkeys pressed */
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#endif
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#ifdef CONFIG_BOARD_TYPES
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unsigned long board_type;
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@ -37,9 +37,9 @@
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* (easy to change)
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*/
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#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
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#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
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#define CONFIG_TRAB 1 /* on a TRAB Board */
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#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
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#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
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#define CONFIG_TRAB 1 /* on a TRAB Board */
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#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
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/* input clock of PLL */
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#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */
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@ -50,6 +50,23 @@
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/***********************************************************
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* I2C stuff:
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* the TRAB is equipped with an ATMEL 24C04 EEPROM at
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* address 0x54 with 8bit addressing
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***********************************************************/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#define CFG_I2C_SPEED 100000 /* I2C speed */
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#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
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#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
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#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* Size of malloc() pool
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*/
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@ -62,13 +79,15 @@
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#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
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#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
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#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
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#define CONFIG_VFD 1 /* VFD linear frame buffer driver */
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#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
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#define CONFIG_HWFLOW /* include RTS/CTS flow control support */
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@ -105,18 +124,30 @@
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#define CONFIG_COMMANDS_ADD_VFD 0
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#endif
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#ifdef CONFIG_DRIVER_S3C24X0_I2C
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#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM
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#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
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#else
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#define CONFIG_COMMANDS_ADD_EEPROM 0
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#define CONFIG_COMMANDS_I2C 0
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#endif
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#ifndef USE_920T_MMU
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
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CFG_CMD_BSP | \
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CFG_CMD_DATE | \
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CONFIG_COMMANDS_ADD_HWFLOW | \
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CONFIG_COMMANDS_ADD_VFD )
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CONFIG_COMMANDS_ADD_VFD | \
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CONFIG_COMMANDS_ADD_EEPROM | \
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CONFIG_COMMANDS_I2C )
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#else
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_BSP | \
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CFG_CMD_DATE | \
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CONFIG_COMMANDS_ADD_HWFLOW | \
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CONFIG_COMMANDS_ADD_VFD )
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CONFIG_COMMANDS_ADD_VFD | \
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CONFIG_COMMANDS_ADD_EEPROM | \
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CONFIG_COMMANDS_I2C )
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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@ -125,8 +156,8 @@
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
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#define CONFIG_PREBOOT "echo;echo *** booting ***;echo"
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#define CONFIG_BOOTARGS "console=ttyS0"
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_BOOTARGS "console=ttyS0"
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.3.68
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#define CONFIG_HOSTNAME trab
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#define CONFIG_SERVERIP 192.168.3.1
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@ -192,6 +223,11 @@
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */
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/* #define CFG_HUSH_PARSER 1 */ /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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@ -200,7 +236,7 @@
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#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0d000000 /* 16 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
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@ -235,11 +271,11 @@
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
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#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
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#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
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/* The following #defines are needed to get flash environment right */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#ifdef CONFIG_POST
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post_run (NULL, POST_RAM | post_bootmode_get(0));
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if (post_bootmode_get(0) & POST_SLOWTEST) {
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post_bootmode_clear();
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board_poweroff();
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}
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#endif
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@ -526,10 +526,7 @@ void board_init_f (ulong bootflag)
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#ifdef CONFIG_POST
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post_bootmode_init();
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if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
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post_run (NULL, POST_ROM | POST_SLOWTEST);
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else
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post_run (NULL, POST_ROM | post_bootmode_get(0));
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post_run (NULL, POST_ROM | post_bootmode_get(0));
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#endif
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WATCHDOG_RESET();
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@ -900,14 +897,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
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#endif
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#ifdef CONFIG_POST
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if (gd->post_hotkeys_latch)
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post_run (NULL, POST_RAM | POST_SLOWTEST);
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else
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post_run (NULL, POST_RAM | post_bootmode_get(0));
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if (post_bootmode_get(0) & POST_SLOWTEST) {
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post_bootmode_clear();
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board_poweroff();
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}
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post_run (NULL, POST_RAM | post_bootmode_get(0));
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
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17
post/post.c
17
post/post.c
@ -65,9 +65,11 @@ void post_bootmode_init (void)
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DECLARE_GLOBAL_DATA_PTR;
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int bootmode = post_bootmode_get (0);
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if (bootmode == 0) {
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if (post_hotkeys_pressed(gd) && !(bootmode & POST_POWERTEST)) {
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bootmode = POST_SLOWTEST;
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} else if (bootmode == 0) {
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bootmode = POST_POWERON;
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} else if (bootmode == POST_POWERON) {
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} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
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bootmode = POST_NORMAL;
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} else {
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return;
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@ -96,11 +98,6 @@ int post_bootmode_get (unsigned int *last_test)
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return bootmode;
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}
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void post_bootmode_clear (void)
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{
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post_word_store (0);
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}
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/* POST tests run before relocation only mark status bits .... */
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static void post_log_mark_start ( unsigned long testid )
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{
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@ -203,6 +200,12 @@ static void post_get_flags (int *test_flags)
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name = s + 1;
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}
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}
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for (j = 0; j < post_list_size; j++) {
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if (test_flags[j] & POST_POWERON) {
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test_flags[j] |= POST_SLOWTEST;
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}
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}
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}
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static int post_run_single (struct post_test *test,
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