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drivers/crypto/fsl: add constructs for protocol descriptors

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Construct APIs are added to create Protocol Descriptors for
CAAM block.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
CC: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Aneesh Bansal 2016-02-15 15:12:56 +05:30 committed by York Sun
parent 6178e95978
commit 2959037077
2 changed files with 52 additions and 0 deletions
drivers/crypto/fsl
desc.hdesc_constr.h

25
drivers/crypto/fsl/desc.h
View File

@ -436,6 +436,31 @@
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
#define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT)
#define OP_PCLID_DSA_VERIFY (0x16 << OP_PCLID_SHIFT)
/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL */
#define OP_PCLID_MP_PUB_KEY (0x14 << OP_PCLID_SHIFT)
#define OP_PCLID_MP_SIGN (0x15 << OP_PCLID_SHIFT)
/* Assuming OP_TYPE = OP_TYPE_ENCAP_PROTOCOL */
#define OP_PCLID_MP_PRIV_KEY (0x14 << OP_PCLID_SHIFT)
/* PROTINFO fields for discrete log public key protocols */
#define OP_PROTINFO_F2M_FP 0x00000001
#define OP_PROTINFO_ECC_DL 0x00000002
#define OP_PROTINFO_ENC_PRI 0x00000004
#define OP_PROTINFO_TEST 0x00000008
#define OP_PROTINFO_EXT_PRI 0x00000010
#define OP_PROTINFO_ENC_Z 0x00000020
#define OP_PROTINFO_EKT_Z 0x00000040
#define OP_PROTINFO_MES_REP 0x00000400
#define OP_PROTINFO_HASH_MD5 0x00000000
#define OP_PROTINFO_HASH_SHA1 0x00000080
#define OP_PROTINFO_HASH_SHA224 0x00000100
#define OP_PROTINFO_HASH_SHA256 0x00000180
#define OP_PROTINFO_HASH_SHA384 0x00000200
#define OP_PROTINFO_HASH_SHA512 0x00000280
/* For non-protocol/alg-only op commands */
#define OP_ALG_TYPE_SHIFT 24

27
drivers/crypto/fsl/desc_constr.h
View File

@ -53,6 +53,19 @@ union ptr_addr_t {
};
#endif
static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
{
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
ptr_addr->m_halfs.high = (u32)(ptr >> 32);
ptr_addr->m_halfs.low = (u32)ptr;
#else
*offset = ptr;
#endif
}
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@ -68,6 +81,11 @@ static inline u32 *desc_end(u32 *desc)
return desc + desc_len(desc);
}
static inline void *desc_pdb(u32 *desc)
{
return desc + 1;
}
static inline void init_desc(u32 *desc, u32 options)
{
*desc = (options | HDR_ONE) + 1;
@ -78,6 +96,15 @@ static inline void init_job_desc(u32 *desc, u32 options)
init_desc(desc, CMD_DESC_HDR | options);
}
static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
{
u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
init_job_desc(desc,
(((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) |
options);
}
static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);