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pcm052: add new BK4r1 target based on PCM052 SoM

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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This commit is contained in:
Albert ARIBAUD \(3ADEV\) 2016-09-26 09:08:08 +02:00 committed by Stefano Babic
parent a7e5f7f3e5
commit 27192d16eb
9 changed files with 298 additions and 60 deletions
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4
arch/arm/Kconfig
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@ -595,6 +595,10 @@ config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
config TARGET_BK4R1
bool "Support BK4r1"
select CPU_V7
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7

3
arch/arm/dts/Makefile
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@ -278,7 +278,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb \
vf610-twr.dtb \
pcm052.dtb
pcm052.dtb \
bk4r1.dtb
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb

48
arch/arm/dts/bk4r1.dts Normal file
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@ -0,0 +1,48 @@
/*
* Copyright 2016 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/dts-v1/;
#include "vf.dtsi"
/ {
model = "Phytec phyCORE-Vybrid";
compatible = "phytec,pcm052", "fsl,vf610";
chosen {
stdout-path = &uart1;
};
aliases {
spi0 = &qspi0;
};
};
&uart1 {
status = "okay";
};
&qspi0 {
bus-num = <0>;
num-cs = <2>;
status = "okay";
qflash0: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <108000000>;
reg = <0>;
};
qflash1: spi_flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <66000000>;
reg = <1>;
};
};

4
arch/arm/dts/vf.dtsi
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@ -83,7 +83,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
reg = <0x40044000 0x1000>,
<0x20000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};

20
board/phytec/pcm052/Kconfig
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@ -17,3 +17,23 @@ config PCM052_DDR_SIZE
default 256
endif
if TARGET_BK4R1
config SYS_BOARD
default "pcm052"
config SYS_VENDOR
default "phytec"
config SYS_SOC
default "vf610"
config SYS_CONFIG_NAME
default "bk4r1"
config PCM052_DDR_SIZE
int
default 512
endif

168
board/phytec/pcm052/pcm052.c
View File

@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
int dram_init(void)
{
static const struct ddr3_jedec_timings pcm052_ddr_timings = {
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 6,
.trrd = 4,
.tccd = 4,
.tbst_int_interval = 4,
.tfaw = 18,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 14040,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tras_lockout = 1,
.tdal = 10,
.bstlen = 3,
.tdll = 512,
.trp_ab = 6,
.tref = 1542,
.trfc = 64,
.tref_int = 5,
.tpdex = 3,
.txpdll = 10,
.txsnr = 68,
.txsr = 506,
.cksrx = 5,
.cksre = 5,
.freq_chg_en = 1,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.zqcs_rotate = 1,
.aprebit = 10,
.cmd_age_cnt = 255,
.age_cnt = 255,
.q_fullness = 0,
.odt_rd_mapcs0 = 1,
.odt_wr_mapcs0 = 1,
.wlmrd = 40,
.wldqsen = 25,
};
static const iomux_v3_cfg_t pcm052_pads[] = {
PCM052_VF610_PAD_DDR_A15__DDR_A_15,
PCM052_VF610_PAD_DDR_A14__DDR_A_14,
@ -256,11 +205,126 @@ int dram_init(void)
PCM052_VF610_PAD_DDR_RESETB,
};
imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
#if defined(CONFIG_TARGET_PCM052)
static const struct ddr3_jedec_timings pcm052_ddr_timings = {
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 6,
.trrd = 4,
.tccd = 4,
.tbst_int_interval = 4,
.tfaw = 18,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 14040,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tras_lockout = 1,
.tdal = 10,
.bstlen = 3,
.tdll = 512,
.trp_ab = 6,
.tref = 1542,
.trfc = 64,
.tref_int = 5,
.tpdex = 3,
.txpdll = 10,
.txsnr = 68,
.txsr = 506,
.cksrx = 5,
.cksre = 5,
.freq_chg_en = 1,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.zqcs_rotate = 1,
.aprebit = 10,
.cmd_age_cnt = 255,
.age_cnt = 255,
.q_fullness = 0,
.odt_rd_mapcs0 = 1,
.odt_wr_mapcs0 = 1,
.wlmrd = 40,
.wldqsen = 25,
};
ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
pcm052_phy_settings, 1, 2);
#elif defined(CONFIG_TARGET_BK4R1)
static const struct ddr3_jedec_timings pcm052_ddr_timings = {
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 6,
.trrd = 4,
.tccd = 4,
.tbst_int_interval = 0,
.tfaw = 16,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 28080,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tras_lockout = 1,
.tdal = 12,
.bstlen = 3,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,
.trfc = 104,
.tref_int = 0,
.tpdex = 3,
.txpdll = 10,
.txsnr = 108,
.txsr = 512,
.cksrx = 5,
.cksre = 5,
.freq_chg_en = 1,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.zqcs_rotate = 1,
.aprebit = 10,
.cmd_age_cnt = 255,
.age_cnt = 255,
.q_fullness = 0,
.odt_rd_mapcs0 = 1,
.odt_wr_mapcs0 = 1,
.wlmrd = 40,
.wldqsen = 25,
};
ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
pcm052_phy_settings, 1, 1);
#else /* Unknown PCM052 variant */
#error DDR characteristics undefined for this target. Please define them.
#endif
imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;

33
configs/bk4r1_defconfig Normal file
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@ -0,0 +1,33 @@
CONFIG_ARM=y
CONFIG_TARGET_BK4R1=y
CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_CMD_DM=y
CONFIG_CMD_UBI=y

33
include/configs/bk4r1.h Normal file
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@ -0,0 +1,33 @@
/*
* Copyright 2016 3ADEV <http://3adev.com>
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* Configuration settings for the phytec PCM-052 SoM-based BK4R1.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Define the BK4r1-specific env commands */
#define PCM052_EXTRA_ENV_SETTINGS \
"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; "
/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
#define PCM052_NET_INIT "run set_gpio122; "
/* add NOR to MTD env */
#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR"
#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
",128k(dtb)"\
",6144k(kernel)"\
",-(root);"\
"NOR:-(nor)"
/* now include standard PCM052 config */
#include "configs/pcm052.h"

45
include/configs/pcm052.h
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@ -52,7 +52,12 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#ifndef MTDIDS_DEFAULT
#define MTDIDS_DEFAULT "nand0=NAND"
#endif
#ifndef MTDPARTS_DEFAULT
#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
@ -61,6 +66,8 @@
",-(root)"
#endif
#endif
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@ -85,7 +92,6 @@
/* QSPI Configs*/
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
@ -115,8 +121,31 @@
#define CONFIG_SYS_TEXT_BASE 0x3f408000
#define CONFIG_BOARD_SIZE_LIMIT 524288
#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS
#define PCM052_EXTRA_ENV_SETTINGS
#endif
/* if no target-specific boot command was defined by the target,
define an empty one */
#ifndef PCM052_BOOTCOMMAND
#define PCM052_BOOTCOMMAND
#endif
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_NET_INIT
#define PCM052_NET_INIT
#endif
/* boot command, including the target-defined one if any */
#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
PCM052_EXTRA_ENV_SETTINGS \
"autoload=no\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"blimg_file=u-boot.vyb\0" \
@ -163,7 +192,8 @@
"nand read ${kernel_addr} kernel; " \
"nand read ${ram_addr} root; " \
"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
"update_bootloader_from_tftp=" PCM052_NET_INIT \
"if tftp ${blimg_addr} "\
"${tftpdir}${blimg_file}; then " \
"mtdparts default; " \
"nand erase.part bootloader; " \
@ -176,7 +206,8 @@
"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
"nand erase.part dtb; " \
"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
"update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
"update_kernel_from_tftp=" PCM052_NET_INIT \
"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
"then setenv fdtsize ${filesize}; " \
"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
"mtdparts default; " \
@ -184,13 +215,15 @@
"nand write ${fdt_addr} dtb ${fdtsize}; " \
"nand erase.part kernel; " \
"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
"update_rootfs_from_tftp=" PCM052_NET_INIT \
"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
"then mtdparts default; " \
"nand erase.part root; " \
"ubi part root; " \
"ubi create rootfs; " \
"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
"update_ramdisk_from_tftp=" PCM052_NET_INIT \
"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
"then mtdparts default; " \
"nand erase.part root; " \
"nand write ${ram_addr} root ${filesize}; fi\0"