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fsl-ddr: make the self refresh idle threshold configurable

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Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Dave Liu 2008-11-21 16:31:35 +08:00 committed by Andrew Fleming-AFLEMING
parent 22ff3d0134
commit 22cca7e1cd
2 changed files with 12 additions and 4 deletions
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12
cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -755,10 +755,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
{
unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
/* Self Refresh Idle Threshold */
ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
}
@ -861,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int i;
unsigned int cas_latency;
unsigned int additive_latency;
unsigned int sr_it;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@ -882,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
? popts->additive_latency_override_value
: common_dimm->additive_latency;
sr_it = (popts->auto_self_refresh_en)
? popts->sr_it
: 0;
/* Chip Select Memory Bounds (CSn_BNDS) */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
phys_size_t sa = 0;
@ -1042,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_wrlvl_cntl(ddr);
set_ddr_pd_cntl(ddr);
set_ddr_sr_cntr(ddr);
set_ddr_sr_cntr(ddr, sr_it);
set_ddr_sdram_rcw_1(ddr);
set_ddr_sdram_rcw_2(ddr);

4
include/asm-ppc/fsl_ddr_sdram.h
View File

@ -146,6 +146,10 @@ typedef struct memctl_options_s {
unsigned int bstopre;
unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
/* Automatic self refresh */
unsigned int auto_self_refresh_en;
unsigned int sr_it;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);