Add initial support for Matrix Vision mvSMR board based on MPC5200B.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
This commit is contained in:
Andre Schwarz
Wolfgang Denk
parent
9acd4f0e91
commit
1f2463d764
2
CREDITS
2
CREDITS
@ -437,7 +437,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor
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N: Andre Schwarz
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E: andre.schwarz@matrix-vision.de
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D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
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D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
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N: Robert Schwebel
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E: r.schwebel@pengutronix.de
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@ -422,6 +422,7 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>
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mvbc_p MPC5200
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mvblm7 MPC8343
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mvsmr MPC5200
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Jon Smirl <jonsmirl@gmail.com>
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1
MAKEALL
1
MAKEALL
@ -70,6 +70,7 @@ LIST_5xxx=" \
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motionpro \
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munices \
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MVBC_P \
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MVSMR \
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o2dnt \
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pcm030 \
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pf5200 \
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5
Makefile
5
Makefile
@ -664,6 +664,11 @@ MVBC_P_config: unconfig
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{ echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; }
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@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
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MVSMR_config: unconfig
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@mkdir -p $(obj)include
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@mkdir -p $(obj)board/matrix_vision/mvsmr
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@$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision
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o2dnt_config: unconfig
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@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
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51
board/matrix_vision/mvsmr/Makefile
Normal file
51
board/matrix_vision/mvsmr/Makefile
Normal file
@ -0,0 +1,51 @@
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004-2008
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# Matrix-Vision GmbH, info@matrix-vision.de
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o fpga.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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@mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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42
board/matrix_vision/mvsmr/bootscript
Normal file
42
board/matrix_vision/mvsmr/bootscript
Normal file
@ -0,0 +1,42 @@
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echo
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echo "==== running autoscript ===="
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echo
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setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
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setenv ramkernel 'setenv kernel_boot ${loadaddr}'
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setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
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setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
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setenv bootfromflash run flashkernel cpird addcons boot24
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setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
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if test ${console} = yes;
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then
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setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
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else
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setenv addcons 'setenv bootargs ${bootargs} console=tty0'
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fi
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setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
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setenv set_static_nm 'setenv netmask ${static_netmask}'
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setenv set_static_gw 'setenv gatewayip ${static_gateway}'
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setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
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if test ${servicemode} != yes;
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then
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echo "=== forced flash mode ==="
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run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
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fi
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if test ${autoscript_boot} != no;
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then
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if test ${netboot} = yes;
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then
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bootp
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if test $? = 0;
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then
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echo "=== bootp succeeded -> netboot ==="
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run set_ip bootfromnet addcons boot24
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else
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echo "=== netboot failed ==="
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fi
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fi
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echo "=== bootfromflash ==="
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run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
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else
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echo "=== boot stopped with autoscript_boot no ==="
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fi
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31
board/matrix_vision/mvsmr/config.mk
Normal file
31
board/matrix_vision/mvsmr/config.mk
Normal file
@ -0,0 +1,31 @@
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifndef TEXT_BASE
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TEXT_BASE = 0xFF800000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
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129
board/matrix_vision/mvsmr/fpga.c
Normal file
129
board/matrix_vision/mvsmr/fpga.c
Normal file
@ -0,0 +1,129 @@
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/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* (C) Copyright 2010
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <spartan3.h>
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#include <command.h>
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#include <asm/io.h>
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#include "fpga.h"
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#include "mvsmr.h"
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Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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0
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};
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Xilinx_desc spartan3 = {
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Xilinx_Spartan2,
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slave_serial,
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XILINX_XC3S200_SIZE,
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(void *) &fpga_fns,
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0,
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};
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DECLARE_GLOBAL_DATA_PTR;
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int mvsmr_init_fpga(void)
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{
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fpga_init();
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fpga_add(fpga_xilinx, &spartan3);
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return 1;
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}
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int fpga_init_fn(int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
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return 0;
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return 1;
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}
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int fpga_done_fn(int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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int result = 0;
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udelay(10);
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if (in_be32(&gpio->simple_ival) & FPGA_DONE)
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result = 1;
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return result;
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}
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int fpga_pgm_fn(int assert, int flush, int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (!assert)
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setbits_8(&gpio->sint_dvo, FPGA_STATUS);
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else
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clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
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return assert;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (assert_clk)
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setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
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else
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clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
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return assert_clk;
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}
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int fpga_wr_fn(int assert_write, int flush, int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (assert_write)
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setbits_be32(&gpio->simple_dvo, FPGA_DIN);
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else
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clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
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return assert_write;
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}
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int fpga_pre_config_fn(int cookie)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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setbits_8(&gpio->sint_dvo, FPGA_STATUS);
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return 0;
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}
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32
board/matrix_vision/mvsmr/fpga.h
Normal file
32
board/matrix_vision/mvsmr/fpga.h
Normal file
@ -0,0 +1,32 @@
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/*
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* (C) Copyright 2008
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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extern int mvsmr_init_fpga(void);
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extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
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extern int fpga_init_fn(int cookie);
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extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
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extern int fpga_wr_fn(int assert_write, int flush, int cookie);
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extern int fpga_done_fn(int cookie);
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extern int fpga_pre_config_fn(int cookie);
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264
board/matrix_vision/mvsmr/mvsmr.c
Normal file
264
board/matrix_vision/mvsmr/mvsmr.c
Normal file
@ -0,0 +1,264 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2005-2010
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
|
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <malloc.h>
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#include <pci.h>
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#include <i2c.h>
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#include <fpga.h>
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#include <environment.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include "fpga.h"
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#include "mvsmr.h"
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#include "../common/mv_common.h"
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#define SDRAM_DDR 1
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x715f0f00
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#define SDRAM_CONFIG1 0xd3722930
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#define SDRAM_CONFIG2 0x46770000
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DECLARE_GLOBAL_DATA_PTR;
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static void sdram_start(int hi_addr)
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{
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long hi_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
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hi_bit);
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/* precharge all banks */
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out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
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hi_bit);
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/* set mode register: extended mode */
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out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
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/* set mode register: reset DLL */
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out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
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/* precharge all banks */
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out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
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hi_bit);
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/* auto refresh */
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out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
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hi_bit);
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/* set mode register */
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out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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/* normal operation */
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out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
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}
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phys_addr_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong test1,
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test2;
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/* setup SDRAM chip selects */
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out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
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/* setup config registers */
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out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else
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dramsize = test2;
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if (dramsize < (1 << 20))
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dramsize = 0;
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if (dramsize > 0)
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out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
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__builtin_ffs(dramsize >> 20) - 1);
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else
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out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
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return dramsize;
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||||
}
|
||||
|
||||
void mvsmr_init_gpio(void)
|
||||
{
|
||||
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
|
||||
struct mpc5xxx_wu_gpio *wu_gpio =
|
||||
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
|
||||
struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
|
||||
|
||||
printf("Ports : 0x%08x\n", gpio->port_config);
|
||||
printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
|
||||
|
||||
out_be32(&gpio->simple_ddr, SIMPLE_DDR);
|
||||
out_be32(&gpio->simple_dvo, SIMPLE_DVO);
|
||||
out_be32(&gpio->simple_ode, SIMPLE_ODE);
|
||||
out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
|
||||
|
||||
out_8(&gpio->sint_ode, SINT_ODE);
|
||||
out_8(&gpio->sint_ddr, SINT_DDR);
|
||||
out_8(&gpio->sint_dvo, SINT_DVO);
|
||||
out_8(&gpio->sint_inten, SINT_INTEN);
|
||||
out_be16(&gpio->sint_itype, SINT_ITYPE);
|
||||
out_8(&gpio->sint_gpioe, SINT_GPIOEN);
|
||||
|
||||
out_8(&wu_gpio->ode, WKUP_ODE);
|
||||
out_8(&wu_gpio->ddr, WKUP_DIR);
|
||||
out_8(&wu_gpio->dvo, WKUP_DO);
|
||||
out_8(&wu_gpio->enable, WKUP_EN);
|
||||
|
||||
out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
|
||||
out_be32(&timers->gpt1.emsr, 0x00000234);
|
||||
out_be32(&timers->gpt2.emsr, 0x00000234);
|
||||
out_be32(&timers->gpt3.emsr, 0x00000234);
|
||||
out_be32(&timers->gpt4.emsr, 0x00000234);
|
||||
out_be32(&timers->gpt5.emsr, 0x00000234);
|
||||
out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
|
||||
out_be32(&timers->gpt7.emsr, 0x00000024);
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *s = getenv("reset_env");
|
||||
|
||||
if (s) {
|
||||
printf(" === FACTORY RESET ===\n");
|
||||
mv_reset_environment();
|
||||
saveenv();
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
void mvsmr_get_dbg_present(void)
|
||||
{
|
||||
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
|
||||
struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
|
||||
|
||||
if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
|
||||
setenv("dbg_present", "no\0");
|
||||
setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
|
||||
} else {
|
||||
setenv("dbg_present", "yes\0");
|
||||
setenv("bootstopkey", "s\0");
|
||||
setbits_8(&psc->command, PSC_RX_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
void mvsmr_get_service_mode(void)
|
||||
{
|
||||
struct mpc5xxx_wu_gpio *wu_gpio =
|
||||
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
|
||||
|
||||
if (in_8(&wu_gpio->ival) & SERVICE_MODE)
|
||||
setenv("servicemode", "no\0");
|
||||
else
|
||||
setenv("servicemode", "yes\0");
|
||||
}
|
||||
|
||||
int mvsmr_get_mac(void)
|
||||
{
|
||||
unsigned char mac[6];
|
||||
struct mpc5xxx_wu_gpio *wu_gpio =
|
||||
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
|
||||
|
||||
if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
|
||||
setenv("lan_present", "no\0");
|
||||
return -1;
|
||||
} else
|
||||
setenv("lan_present", "yes\0");
|
||||
|
||||
i2c_read(0x50, 0, 1, mac, 6);
|
||||
|
||||
eth_setenv_enetaddr("ethaddr", mac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
mvsmr_init_gpio();
|
||||
printf("Board: Matrix Vision mvSMR\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flash_preinit(void)
|
||||
{
|
||||
/*
|
||||
* Now, when we are in RAM, enable flash write
|
||||
* access for detection process.
|
||||
* Note that CS_BOOT cannot be cleared when
|
||||
* executing in flash.
|
||||
*/
|
||||
clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
|
||||
}
|
||||
|
||||
void flash_afterinit(ulong size)
|
||||
{
|
||||
out_be32((u32 *)MPC5XXX_BOOTCS_START,
|
||||
START_REG(CONFIG_SYS_BOOTCS_START | size));
|
||||
out_be32((u32 *)MPC5XXX_CS0_START,
|
||||
START_REG(CONFIG_SYS_BOOTCS_START | size));
|
||||
out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
|
||||
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
|
||||
out_be32((u32 *)MPC5XXX_CS0_STOP,
|
||||
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
|
||||
}
|
||||
|
||||
struct pci_controller hose;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
mvsmr_get_dbg_present();
|
||||
mvsmr_get_service_mode();
|
||||
mvsmr_init_fpga();
|
||||
mv_load_fpga();
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
if (!mvsmr_get_mac())
|
||||
return cpu_eth_init(bis);
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
43
board/matrix_vision/mvsmr/mvsmr.h
Normal file
43
board/matrix_vision/mvsmr/mvsmr.h
Normal file
@ -0,0 +1,43 @@
|
||||
#include <pci.h>
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
|
||||
#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
|
||||
#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
|
||||
#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
|
||||
#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
|
||||
#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
|
||||
#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
|
||||
#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
|
||||
#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
|
||||
#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
|
||||
|
||||
#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
|
||||
#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
|
||||
#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
|
||||
#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
|
||||
#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
|
||||
#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
|
||||
#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
|
||||
#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
|
||||
|
||||
#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
|
||||
S_FPGA_CCLK)
|
||||
#define SIMPLE_DVO (FPGA_CONFIG)
|
||||
#define SIMPLE_ODE (FPGA_CONFIG)
|
||||
#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
|
||||
S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
|
||||
|
||||
#define SINT_ODE 0x1
|
||||
#define SINT_DDR 0x3
|
||||
#define SINT_DVO 0x1
|
||||
#define SINT_INTEN 0
|
||||
#define SINT_ITYPE 0
|
||||
#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
|
||||
|
||||
#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
|
||||
#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
|
||||
#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
|
||||
#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
|
||||
FLASH_RBY | UART_EN1 | LAN_PRSNT)
|
||||
138
board/matrix_vision/mvsmr/u-boot.lds
Normal file
138
board/matrix_vision/mvsmr/u-boot.lds
Normal file
@ -0,0 +1,138 @@
|
||||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* (C) Copyright 2010
|
||||
* André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the first two sectors (=8KB) of our S29GL flash chip */
|
||||
cpu/mpc5xxx/start.o (.text)
|
||||
cpu/mpc5xxx/traps.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/cache.o (.text)
|
||||
lib_ppc/time.o (.text)
|
||||
|
||||
/* This is only needed to force failure if size of above code will ever */
|
||||
/* increase and grow into reserved space. */
|
||||
. = ALIGN(0x2000); /* location counter has to be 0x4000 now */
|
||||
. += 0x4000; /* ->0x8000, i.e. move to env_offset */
|
||||
|
||||
. = env_offset; /* ld error as soon as above ALIGN misplaces lc */
|
||||
common/env_embedded.o (.ppcenv)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
55
doc/README.mvsmr
Normal file
55
doc/README.mvsmr
Normal file
@ -0,0 +1,55 @@
|
||||
Matrix Vision mvSMR
|
||||
-------------------
|
||||
|
||||
1. Board Description
|
||||
|
||||
The mvSMR is a 75x130mm single image processing board used
|
||||
in automation. Power Supply is 24VDC.
|
||||
|
||||
2 System Components
|
||||
|
||||
2.1 CPU
|
||||
Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
|
||||
64MB DDR-I @ 133MHz.
|
||||
8 MByte Nor Flash on local bus.
|
||||
2 serial ports. Console running on ttyS0 @ 115200 8N1.
|
||||
|
||||
2.2 PCI
|
||||
PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
|
||||
|
||||
2.3 FPGA
|
||||
Xilinx Spartan-3 XC3S200 with PCI DMA engine.
|
||||
Connects to Matrix Vision specific CCD/CMOS sensor interface.
|
||||
|
||||
2.4 I2C
|
||||
EEPROM @ 0xA0 for vendor specifics.
|
||||
image sensor interface (slave adresses depend on sensor)
|
||||
|
||||
3 Flash layout.
|
||||
|
||||
reset vector is 0x00000100, i.e. "LOWBOOT".
|
||||
|
||||
FF800000 u-boot
|
||||
FF806000 u-boot script image
|
||||
FF808000 u-boot environment
|
||||
FF840000 FPGA raw bit file
|
||||
FF880000 root FS
|
||||
FFF00000 kernel
|
||||
|
||||
4 Booting
|
||||
|
||||
On startup the bootscript @ FF806000 is executed. This script can be
|
||||
exchanged easily. Default boot mode is "boot from flash", i.e. system
|
||||
works stand-alone.
|
||||
|
||||
This behaviour depends on some environment variables :
|
||||
|
||||
"netboot" : yes ->try dhcp/bootp and boot from network.
|
||||
A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
|
||||
DHCP server configuration, e.g. to provide different images to
|
||||
different devices.
|
||||
|
||||
During netboot the system tries to get 3 image files:
|
||||
1. Kernel - name + data is given during BOOTP.
|
||||
2. Initrd - name is stored in "initrd_name"
|
||||
Fallback files are the flash versions.
|
||||
295
include/configs/MVSMR.h
Normal file
295
include/configs/MVSMR.h
Normal file
@ -0,0 +1,295 @@
|
||||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2004-2010
|
||||
* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <version.h>
|
||||
|
||||
#define CONFIG_MPC5xxx 1
|
||||
#define CONFIG_MPC5200 1
|
||||
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
|
||||
|
||||
#define BOOTFLAG_COLD 0x01
|
||||
#define BOOTFLAG_WARM 0x02
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 5
|
||||
#endif
|
||||
|
||||
#define CONFIG_PSC_CONSOLE 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
|
||||
230400}
|
||||
|
||||
#define CONFIG_PCI 1
|
||||
#define CONFIG_PCI_PNP 1
|
||||
#undef CONFIG_PCI_SCAN_SHOW
|
||||
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_SYS_XLB_PIPELINING 1
|
||||
#define CONFIG_HIGH_BATS 1
|
||||
|
||||
#define MV_CI mvSMR
|
||||
#define MV_VCI mvSMR
|
||||
#define MV_FPGA_DATA 0xff840000
|
||||
#define MV_FPGA_SIZE 0x1ff88
|
||||
#define MV_KERNEL_ADDR 0xfff00000
|
||||
#define MV_SCRIPT_ADDR 0xff806000
|
||||
#define MV_INITRD_ADDR 0xff880000
|
||||
#define MV_INITRD_LENGTH 0x00240000
|
||||
#define MV_SCRATCH_ADDR 0xffcc0000
|
||||
#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
|
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1
|
||||
|
||||
#define MV_KERNEL_ADDR_RAM 0x00100000
|
||||
#define MV_INITRD_ADDR_RAM 0x00400000
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_FPGA
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_NTPSERVER
|
||||
#define CONFIG_BOOTP_RANDOM_DELAY
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_VENDOREX
|
||||
|
||||
/*
|
||||
* Autoboot
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "source ${script_addr}"
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
|
||||
" allocate=6M"
|
||||
|
||||
#define XMK_STR(x) #x
|
||||
#define MK_STR(x) XMK_STR(x)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console_nr=0\0" \
|
||||
"console=no\0" \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" \
|
||||
"fpga=0\0" \
|
||||
"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
|
||||
"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
|
||||
"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
|
||||
"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
|
||||
"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
|
||||
"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
|
||||
"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
|
||||
"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
|
||||
"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
|
||||
"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
|
||||
"mv_version=" U_BOOT_VERSION "\0" \
|
||||
"dhcp_client_id=" MK_STR(MV_CI) "\0" \
|
||||
"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
|
||||
"netretry=no\0" \
|
||||
"use_static_ipaddr=no\0" \
|
||||
"static_ipaddr=192.168.0.101\0" \
|
||||
"static_netmask=255.255.255.0\0" \
|
||||
"static_gateway=0.0.0.0\0" \
|
||||
"initrd_name=uInitrd.mvsmr-rfs\0" \
|
||||
"zcip=yes\0" \
|
||||
"netboot=no\0" \
|
||||
""
|
||||
|
||||
#undef XMK_STR
|
||||
#undef MK_STR
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#undef CONFIG_FLASH_16BIT
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_SYS_LOWBOOT
|
||||
#define CONFIG_SYS_FLASH_BASE TEXT_BASE
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x00800000
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#undef CONFIG_SYS_FLASH_PROTECTION
|
||||
#define CONFIG_HAS_UID
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
#define CONFIG_ENV_OFFSET 0x8000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000
|
||||
|
||||
/* used by linker script to wrap code around */
|
||||
#define CONFIG_SCRIPT_OFFSET 0x6000
|
||||
#define CONFIG_SCRIPT_SECT_SIZE 0x2000
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xF0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_MODULE 1
|
||||
#define CONFIG_SYS_I2C_SPEED 86000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
|
||||
#define CONFIG_MPC5xxx_FEC
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
#define CONFIG_NETDEV eth0
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#undef CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "=> "
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00800000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x02f00000
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* default load address */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x02000000
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 0x00200000
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x00047800
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x000000f0
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x00000100
|
||||
|
||||
#undef FPGA_DEBUG
|
||||
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
|
||||
#define CONFIG_FPGA_XILINX 1
|
||||
#define CONFIG_FPGA_SPARTAN2 1
|
||||
#define CONFIG_FPGA_COUNT 1
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user