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Merge branch '2021-12-27-CONFIG-migrations' into next

Browse Source 
- Merge a large number of CONFIG migration patches.  Most of these are
  taking existing migrations and re-running them.  A few of these needed
  additional minor conversions done first, so that more complex
  dependencies could be expressed.  In the end we now have CI jobs to
  ensure that no migrated symbols are used in board config header files.
This commit is contained in:
Tom Rini 2021-12-27 17:20:21 -05:00
commit 111a8b5735
858 changed files with 1641 additions and 3999 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
.azure-pipelines.yml
View File

@ -49,6 +49,33 @@ jobs:
-j$(sysctl -n hw.logicalcpu)
displayName: 'Perform tools-only build'
- job: check_for_migrated_symbols_in_board_header
displayName: 'Check for migrated symbols in board header'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
KSYMLST=`mktemp`
KUSEDLST=`mktemp`
cat `find . -name "Kconfig*"` | \
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
| sort -u > $KSYMLST
for CFG in `find include/configs -name "*.h"`; do
grep '#define[[:blank:]]CONFIG_' $CFG | \
sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' | \
sort -u > ${KUSEDLST} || true
NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
cut -d , -f 3`
if [[ $NUM -ne 0 ]]; then
echo "Unmigrated symbols found in $CFG"
exit 1
fi
done
- job: cppcheck
displayName: 'Static code analysis with cppcheck'
pool:

21
.gitlab-ci.yml
View File

@ -105,6 +105,27 @@ build all other platforms:
exit $ret;
fi;
check for migrated symbols in board header:
stage: testsuites
script:
- KSYMLST=`mktemp`;
KUSEDLST=`mktemp`;
cat `find . -name "Kconfig*"` |
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
| sort -u > $KSYMLST;
for CFG in `find include/configs -name "*.h"`; do
grep '#define[[:blank:]]CONFIG_' $CFG |
sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |
sort -u > ${KUSEDLST} || true;
NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
cut -d , -f 3`;
if [[ $NUM -ne 0 ]]; then
echo "Unmigrated symbols found in $CFG";
exit 1;
fi;
done
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
cppcheck:

46
README
View File

@ -565,11 +565,6 @@ The following options need to be configured:
boards with QUICC Engines require OF_QE to set UCC MAC
addresses
CONFIG_OF_BOARD_SETUP
Board code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel
CONFIG_OF_SYSTEM_SETUP
Other code has addition modification that it wants to make
@ -596,9 +591,6 @@ The following options need to be configured:
Note: If a "bootargs" environment is defined, it will override
the defaults discussed just above.
- Cache Configuration:
CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
- Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
@ -647,20 +639,6 @@ The following options need to be configured:
example "env grep" and "setexpr".
- Watchdog:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
support for the SoC. There must be support in the SoC
specific code for a watchdog. For the 8xx
CPUs, the SIU Watchdog feature is enabled in the SYPCR
register. When supported for a specific SoC is
available, then no further board specific code should
be needed to use it.
CONFIG_HW_WATCHDOG
When using a watchdog circuitry external to the used
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
CONFIG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
@ -1021,9 +999,6 @@ The following options need to be configured:
sending again an USB request to the device.
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
@ -1520,16 +1495,6 @@ The following options need to be configured:
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
CONFIG_SOFT_SPI
Enables a software (bit-bang) SPI driver rather than
using hardware support. This is a general purpose
driver that only requires three general I/O port pins
(two outputs, one input) to function. If this is
defined, the board configuration must define several
SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h.
CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
@ -1595,13 +1560,6 @@ The following options need to be configured:
Time to wait after FPGA configuration. The default is
200 ms.
- Configuration Management:
CONFIG_IDENT_STRING
If defined, this string will be added to the U-Boot
version information (U_BOOT_VERSION)
- Vendor Parameter Protection:
U-Boot considers the values of the environment
@ -1922,10 +1880,6 @@ The following options need to be configured:
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)

16
arch/Kconfig
View File

@ -1,3 +1,7 @@
config ARCH_MAP_SYSMEM
depends on SANDBOX || NDS32
def_bool y
config CREATE_ARCH_SYMLINK
bool
@ -353,6 +357,18 @@ config SYS_DISABLE_DCACHE_OPS
Note that, its up to the individual architectures to implement
this functionality.
config SYS_IMMR
hex
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default SYS_CCSRBAR_DEFAULT
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of many Freescale / NXP SoCs.
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || NDS32 || MIPS || RISCV

3
arch/arc/lib/cpu.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
#include <vsprintf.h>
@ -18,7 +19,7 @@ int arch_cpu_init(void)
{
timer_init();
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->cpu_clk = get_board_sys_clk();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
cache_init();

16
arch/arm/Kconfig
View File

@ -311,6 +311,10 @@ config CPU_PXA
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config CPU_PXA27X
bool
select CPU_PXA
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
@ -1767,7 +1771,7 @@ config TARGET_SL28
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
select CPU_PXA27X
select GPIO_EXTRA_HEADER
config ARCH_UNIPHIER
@ -1909,6 +1913,7 @@ config ARCH_OCTEONTX
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE
config ARCH_OCTEONTX2
@ -1921,6 +1926,7 @@ config ARCH_OCTEONTX2
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE
config TARGET_THUNDERX_88XX
@ -2046,6 +2052,14 @@ config ISW_ENTRY_ADDR
image headers.
endif
config SYS_KWD_CONFIG
string "kwbimage config file path"
depends on ARCH_KIRKWOOD || ARCH_MVEBU
default "arch/arm/mach-mvebu/kwbimage.cfg"
help
Path within the source directory to the kwbimage.cfg file to use
when packaging the U-Boot image for use.
source "arch/arm/mach-apple/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"

11
arch/arm/cpu/arm920t/ep93xx/speed.c
View File

@ -6,12 +6,13 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
/*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
* get_board_sys_clk() should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
@ -20,14 +21,14 @@
/*
* return the PLL output frequency
*
* PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
* PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
* / (X2IPD + 1) / 2^PS
*/
static ulong get_PLLCLK(uint32_t *pllreg)
{
uint8_t i;
const uint32_t clkset = readl(pllreg);
uint64_t rate = CONFIG_SYS_CLK_FREQ;
uint64_t rate = get_board_sys_clk();
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
@ -87,9 +88,9 @@ ulong get_UCLK(void)
const uint32_t value = readl(&syscon->pwrcnt);
if (value & SYSCON_PWRCNT_UART_BAUD)
uclk_rate = CONFIG_SYS_CLK_FREQ;
uclk_rate = get_board_sys_clk();
else
uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
uclk_rate = get_board_sys_clk() / 2;
return uclk_rate;
}

5
arch/arm/cpu/arm920t/imx/speed.c
View File

@ -7,13 +7,14 @@
#include <common.h>
#if defined (CONFIG_IMX)
#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
* get_board_sys_clk() should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
@ -45,7 +46,7 @@ ulong get_mcuPLLCLK(void)
mfi = mfi<=5 ? 5 : mfi;
return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)

1
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -1,5 +1,6 @@
config ARCH_LS1021A
bool
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008378

2
arch/arm/cpu/armv7/ls102xa/clock.c
View File

@ -39,7 +39,7 @@ void get_sys_info(struct sys_info *sys_info)
uint i;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
unsigned long sysclk = get_board_sys_clk();
sys_info->freq_systembus = sysclk;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)

4
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -131,9 +131,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
sysclk_path = fdt_get_alias(blob, "sysclk");
if (sysclk_path)
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
CONFIG_SYS_CLK_FREQ, 1);
get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
"clock-frequency", get_board_sys_clk(), 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000

13
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -41,6 +41,7 @@ config ARCH_LS1028A
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select FSL_TZASC_1
select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@ -59,6 +60,7 @@ config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
@ -94,6 +96,7 @@ config ARCH_LS1043A
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
@ -134,6 +137,7 @@ config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
@ -182,6 +186,7 @@ config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
@ -237,6 +242,7 @@ config ARCH_LX2162A
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
select FSL_TZPC_BP147
select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
@ -256,6 +262,7 @@ config ARCH_LX2162A
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@ -273,6 +280,7 @@ config ARCH_LX2160A
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
select FSL_TZPC_BP147
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
@ -294,6 +302,7 @@ config ARCH_LX2160A
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@ -521,10 +530,6 @@ endmenu
menu "Layerscape clock tree configuration"
depends on FSL_LSCH2 || FSL_LSCH3
config SYS_FSL_CLK
bool "Enable clock tree initialization"
default y
config CLUSTER_CLK_FREQ
int "Reference clock of core cluster"
depends on ARCH_LS1012A

1
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <fsl_ddr_sdram.h>

4
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -161,7 +161,7 @@ void fsl_fdt_disable_usb(void *blob)
* controller is used, SYSCLK must meet the additional requirement
* of 100 MHz.
*/
if (CONFIG_SYS_CLK_FREQ != 100000000) {
if (get_board_sys_clk() != 100000000) {
off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
while (off != -FDT_ERR_NOTFOUND) {
fdt_status_disabled(blob, off);
@ -655,7 +655,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
CONFIG_SYS_CLK_FREQ, 1);
get_board_sys_clk(), 1);
#ifdef CONFIG_GIC_V3_ITS
ls_gic_rd_tables_init(blob);

4
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -52,12 +52,12 @@ void get_sys_info(struct sys_info *sys_info)
uint i, cluster;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
unsigned long sysclk = get_board_sys_clk();
unsigned long cluster_clk;
sys_info->freq_systembus = sysclk;
#ifndef CONFIG_CLUSTER_CLK_FREQ
#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_CLUSTER_CLK_FREQ get_board_sys_clk()
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;

2
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -72,7 +72,7 @@ void get_sys_info(struct sys_info *sys_info)
#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
unsigned long sysclk = get_board_sys_clk();
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;

1
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <image.h>
#include <log.h>

4
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -93,7 +93,9 @@ void board_init_f(ulong dummy)
i2c_init_all();
#endif
#endif
#ifdef CONFIG_VID
#if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LX2160A) || \
defined(CONFIG_ARCH_LX2162A))
init_func_vid();
#endif
dram_init();

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -234,7 +234,6 @@
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -11,7 +11,6 @@
#include <linux/bitops.h>
#endif
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -9,7 +9,6 @@
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000

1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -11,7 +11,6 @@
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)

3
arch/arm/mach-apple/Kconfig
View File

@ -15,4 +15,7 @@ config SYS_MALLOC_LEN
config SYS_MALLOC_F_LEN
default 0x4000
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default SYS_TEXT_BASE
endif

6
arch/arm/mach-davinci/cpu.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <asm/arch/hardware.h>
#include <asm/global_data.h>
@ -91,3 +92,8 @@ int set_cpu_clk_info(void)
gd->bd->bi_dsp_freq = 0;
return 0;
}
unsigned long get_board_sys_clk(void)
{
return clk_get(DAVINCI_ARM_CLKID);
}

5
arch/arm/mach-exynos/clock.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@ -136,7 +137,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
/* SDIV [2:0] */
s = r & 0x7;
freq = CONFIG_SYS_CLK_FREQ;
freq = get_board_sys_clk();
if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
@ -1051,7 +1052,7 @@ static unsigned long exynos5800_get_lcd_clk(void)
RPLL};
sclk = get_pll_clk(reg_map[sel]);
} else
sclk = CONFIG_SYS_CLK_FREQ;
sclk = get_board_sys_clk();
/*
* CLK_DIV_DISP10
* FIMD1_RATIO [3:0]

1
arch/arm/mach-imx/imxrt/Kconfig
View File

@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
bool

49
arch/arm/mach-kirkwood/Kconfig
View File

@ -1,66 +1,115 @@
if ARCH_KIRKWOOD
config FEROCEON_88FR131
bool
config KW88F6192
bool
config KW88F6281
bool
config SHEEVA_88SV131
bool
choice
prompt "Marvell Kirkwood board select"
optional
config TARGET_OPENRD
bool "Marvell OpenRD Board"
select KW88F6281
select SHEEVA_88SV131
config TARGET_DREAMPLUG
bool "DreamPlug Board"
select KW88F6281
select SHEEVA_88SV131
config TARGET_DS109
bool "Synology DS109"
select KW88F6281
select SHEEVA_88SV131
config TARGET_GURUPLUG
bool "GuruPlug Board"
select KW88F6281
select SHEEVA_88SV131
config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_LSXL
bool "lsxl Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_POGO_E02
bool "pogo_e02 Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_DNS325
bool "dns325 Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_ICONNECT
bool "iconnect Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_KM_KIRKWOOD
bool "KM Kirkwood Board"
select FEROCEON_88FR131
select KW88F6281
select VENDOR_KM
config TARGET_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
select FEROCEON_88FR131
config TARGET_IB62X0
bool "ib62x0 Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_DOCKSTAR
bool "Dockstar Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_GOFLEXHOME
bool "GoFlex Home Board"
select FEROCEON_88FR131
select KW88F6281
config TARGET_NAS220
bool "BlackArmor NAS220"
select FEROCEON_88FR131
select KW88F6192
config TARGET_NSA310S
bool "Zyxel NSA310S"
select FEROCEON_88FR131
select KW88F6192
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
select FEROCEON_88FR131
select KW88F6281
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
select FEROCEON_88FR131
select KW88F6281
endchoice

9
arch/arm/mach-kirkwood/include/mach/config.h
View File

@ -27,15 +27,6 @@
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
/*
* By default kwbimage.cfg from board specific folder is used
* If for some board, different configuration file need to be used,
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000

9
arch/arm/mach-mvebu/include/mach/config.h
View File

@ -27,15 +27,6 @@
#define CONFIG_SYS_L2_PL310
/*
* By default the generated mvebu kwbimage.cfg is used
* If for some board, different configuration file need to be used,
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000

14
arch/arm/mach-nexell/Kconfig
View File

@ -33,6 +33,12 @@ config TARGET_NANOPI2
endchoice
config SYS_PLLFIN
int
config TIMER_SYS_TICK_CH
int
config SYS_BOARD
default "nanopi2"
@ -45,13 +51,13 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "s5p4418_nanopi2"
endmenu
config SYS_PLLFIN
int
default 24000000
config TIMER_SYS_TICK_CH
int
default 0
endmenu
source "board/friendlyarm/Kconfig"

4
arch/arm/mach-octeontx/Kconfig
View File

@ -16,8 +16,4 @@ config SYS_SOC
string
default "octeontx"
config SYS_PCI_64BIT
bool
default y
endif

4
arch/arm/mach-octeontx2/Kconfig
View File

@ -16,8 +16,4 @@ config SYS_SOC
string
default "octeontx2"
config SYS_PCI_64BIT
bool
default y
endif

8
arch/arm/mach-orion5x/Kconfig
View File

@ -1,11 +1,19 @@
if ARCH_ORION5X
config 88F5182
bool
config FEROCEON
bool
choice
prompt "Marvell Orion board select"
optional
config TARGET_EDMINIV2
bool "LaCie Ethernet Disk mini V2"
select 88F5182
select FEROCEON
select SUPPORT_SPL
endchoice

6
arch/arm/mach-rockchip/Kconfig
View File

@ -8,7 +8,6 @@ config ROCKCHIP_PX30
select SPL
select TPL
select TPL_TINY_FRAMEWORK if TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL
@ -80,7 +79,6 @@ config ROCKCHIP_RK322X
select TPL
select TPL_DM
select TPL_OF_LIBFDT
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_DRIVERS_MISC
imply ROCKCHIP_COMMON_BOARD
@ -112,7 +110,6 @@ config ROCKCHIP_RK3288
imply TPL_DRIVERS_MISC
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_NEEDS_SEPARATE_TEXT_BASE
imply TPL_NEEDS_SEPARATE_STACK
imply TPL_OF_CONTROL
imply TPL_OF_PLATDATA
@ -160,7 +157,6 @@ config ROCKCHIP_RK3328
select SPL
select SUPPORT_TPL
select TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
@ -183,7 +179,6 @@ config ROCKCHIP_RK3368
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
@ -216,7 +211,6 @@ config ROCKCHIP_RK3399
select SPL_RAM if SPL
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL

12
arch/arm/mach-s5pc1xx/clock.c
View File

@ -14,12 +14,8 @@
#define CLK_D 1
#define CLK_P 2
#ifndef CONFIG_SYS_CLK_FREQ_C100
#define CONFIG_SYS_CLK_FREQ_C100 12000000
#endif
#ifndef CONFIG_SYS_CLK_FREQ_C110
#define CONFIG_SYS_CLK_FREQ_C110 24000000
#endif
#define CFG_SYS_CLK_FREQ_C100 12000000
#define CFG_SYS_CLK_FREQ_C110 24000000
/* s5pc110: return pll clock frequency */
static unsigned long s5pc100_get_pll_clk(int pllreg)
@ -66,7 +62,7 @@ static unsigned long s5pc100_get_pll_clk(int pllreg)
s = r & 0x7;
/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
freq = CONFIG_SYS_CLK_FREQ_C100;
freq = CFG_SYS_CLK_FREQ_C100;
fout = m * (freq / (p * (1 << s)));
return fout;
@ -116,7 +112,7 @@ static unsigned long s5pc110_get_pll_clk(int pllreg)
/* SDIV [2:0] */
s = r & 0x7;
freq = CONFIG_SYS_CLK_FREQ_C110;
freq = CFG_SYS_CLK_FREQ_C110;
if (pllreg == APLL) {
if (s < 1)
s = 1;

6
arch/arm/mach-zynqmp-r5/Kconfig
View File

@ -21,6 +21,12 @@ config SYS_CONFIG_NAME
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
config CPU_FREQ_HZ
int "CPU frequency"
default 800000000
help
The value, in Hz, that the CPU clock is running at.
config SYS_MALLOC_F_LEN
default 0x600

1
arch/m68k/Kconfig
View File

@ -128,6 +128,7 @@ config TARGET_COBRA5272
config TARGET_EB_CPU5282
bool "Support eb_cpu5282"
select M5282
select HW_WATCHDOG
config TARGET_M5208EVBE
bool "Support M5208EVBE"

9
arch/nds32/cpu/n1213/ag101/timer.c
View File

@ -9,6 +9,7 @@
*/
#ifndef CONFIG_TIMER
#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
@ -76,7 +77,7 @@ void reset_timer_masked(void)
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
lastdec = readl(&tmr->timer3_counter) /
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
timestamp = 0; /* start "advancing" time stamp from 0 */
@ -101,7 +102,7 @@ ulong get_timer_masked(void)
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
ulong now = readl(&tmr->timer3_counter) /
(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
@ -155,7 +156,7 @@ void __udelay(unsigned long usec)
#ifdef CONFIG_FTTMR010_EXT_CLK
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
#else
long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
#endif
unsigned long now, last = readl(&tmr->timer3_counter);
@ -190,7 +191,7 @@ ulong get_tbclk(void)
#ifdef CONFIG_FTTMR010_EXT_CLK
return CONFIG_SYS_HZ;
#else
return CONFIG_SYS_CLK_FREQ;
return get_board_sys_clk();
#endif
}
#endif /* CONFIG_TIMER */

14
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -179,13 +179,6 @@ config ARCH_MPC837X
select SYS_CACHE_SHIFT_5
select FSL_ELBC
config SYS_IMMR
hex "Value for IMMR"
default 0xE0000000
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of the SoC.
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
@ -195,6 +188,13 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
config 83XX_PCICLK
hex "PCI clock frequency"
default 0xDEADBEEF
help
If required, the PCI clock frequency to use when configuring
the host bridge.
config FSL_ELBC
bool

3
arch/powerpc/cpu/mpc83xx/pcie.c
View File

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/global_data.h>
@ -46,7 +47,7 @@ int get_pcie_clk(int index)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
sccr = im->clk.sccr;
pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

4
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -137,8 +137,8 @@ int get_clocks(void)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_SYS_CLK_FREQ)
pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#if CONFIG_SYS_CLK_FREQ != 0
pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif

2
arch/powerpc/cpu/mpc83xx/spl_minimal.c
View File

@ -102,5 +102,5 @@ ulong get_bus_freq(ulong dummy)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
return CONFIG_SYS_CLK_FREQ * spmf;
return get_board_sys_clk() * spmf;
}

5
arch/powerpc/cpu/mpc83xx/start.S
View File

@ -14,8 +14,6 @@
#include <config.h>
#include <mpc83xx.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@ -115,9 +113,6 @@ disable_addr_trans:
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
#ifndef CONFIG_SYS_IMMR
#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the

7
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -354,6 +354,7 @@ config ARCH_P1010
bool
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_HAS_SERDES
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@ -1001,6 +1002,9 @@ config SYS_FSL_ERRATUM_SRIO_A004034
config SYS_FSL_ERRATUM_USB14
bool
config SYS_HAS_SERDES
bool
config SYS_P4080_ERRATUM_CPU22
bool
@ -1084,9 +1088,6 @@ config SYS_PPC64
config SYS_PPC_E500_USE_DEBUG_TLB
bool
config FSL_IFC
bool
config FSL_ELBC
bool

4
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -662,9 +662,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
"clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
"clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else

8
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -75,7 +75,7 @@ void get_sys_info(sys_info_t *sys_info)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
unsigned long sysclk = get_board_sys_clk();
uint mem_pll_rat;
sys_info->freq_systembus = sysclk;
@ -102,7 +102,7 @@ void get_sys_info(sys_info_t *sys_info)
* are driven by differential sysclock.
*/
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
sys_info->freq_ddrbus = get_board_sys_clk();
else
#endif
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
@ -526,7 +526,7 @@ void get_sys_info(sys_info_t *sys_info)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
@ -554,7 +554,7 @@ void get_sys_info(sys_info_t *sys_info)
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
sys_info->freq_qe = qe_ratio * get_board_sys_clk();
#endif
#endif

3
arch/powerpc/cpu/mpc8xx/Kconfig
View File

@ -84,9 +84,6 @@ config SYS_DER
help
Debug Event Register (37-47)
config SYS_IMMR
hex "Value for IMMR"
source "board/cssi/MCR3000/Kconfig"
endmenu

3
arch/sandbox/Kconfig
View File

@ -1,9 +1,6 @@
menu "Sandbox architecture"
depends on SANDBOX
config ARCH_MAP_SYSMEM
def_bool y
config SYS_ARCH
default "sandbox"

6
arch/sh/Kconfig
View File

@ -4,13 +4,17 @@ menu "SuperH architecture"
config CPU_SH4
bool
config CPU_SH7751
bool
select CPU_SH4
choice
prompt "Target select"
optional
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
select CPU_SH7751
endchoice

2
arch/sh/include/asm/config.h
View File

@ -11,6 +11,6 @@
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
#endif

9
arch/xtensa/lib/time.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <time.h>
#include <asm/global_data.h>
#include <linux/delay.h>
@ -51,7 +52,7 @@ static void delay_cycles(unsigned cycles)
void __udelay(unsigned long usec)
{
ulong lo, hi, i;
ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
ulong mhz = get_board_sys_clk() / 1000000;
/* Scale to support full 32-bit usec range */
@ -74,7 +75,7 @@ ulong get_timer(ulong base)
#if XCHAL_HAVE_CCOUNT
register ulong ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
return ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#else
/*
* Add at least the overhead of this call (in cycles).
@ -85,7 +86,7 @@ ulong get_timer(ulong base)
*/
fake_ccount += 20;
return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
return fake_ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#endif
}
@ -114,6 +115,6 @@ unsigned long timer_get_us(void)
unsigned long ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
return ccount / (get_board_sys_clk() / 1000000);
}
#endif

11
board/LaCie/net2big_v2/Kconfig
View File

@ -1,5 +1,16 @@
if TARGET_NET2BIG_V2
choice
prompt "Board variant"
config D2NET_V2
bool "D2NET v2"
config NET2BIG_V2
bool "NET2BIG v2"
endchoice
config SYS_BOARD
default "net2big_v2"

25
board/LaCie/netspace_v2/Kconfig
View File

@ -1,5 +1,30 @@
if TARGET_NETSPACE_V2
choice
prompt "Board variant"
config INETSPACE_V2
bool "INETSPACE v2"
select KW88F6281
config NETSPACE_LITE_V2
bool "NETSPACE LITE v2"
select KW88F6192
config NETSPACE_MAX_V2
bool "NETSPACE MAX v2"
select KW88F6281
config NETSPACE_MINI_V2
bool "NETSPACE MINI v2"
select KW88F6192
config NETSPACE_V2
bool "NETSPACE v2"
select KW88F6281
endchoice
config SYS_BOARD
default "netspace_v2"

14
board/Marvell/openrd/Kconfig
View File

@ -1,5 +1,19 @@
if TARGET_OPENRD
choice
prompt "Board variant"
config BOARD_IS_OPENRD_BASE
bool "Base"
config BOARD_IS_OPENRD_CLIENT
bool "Client"
config BOARD_IS_OPENRD_ULTIMATE
bool "Ultimate"
endchoice
config SYS_BOARD
default "openrd"

13
board/cadence/xtfpga/xtfpga.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <dm.h>
#include <init.h>
@ -49,7 +50,7 @@ int checkboard(void)
return 0;
}
int board_postclk_init(void)
unsigned long get_board_sys_clk(void)
{
/*
* Obtain CPU clock frequency from board and cache in global
@ -58,11 +59,17 @@ int board_postclk_init(void)
*/
#ifdef CONFIG_SYS_FPGAREG_FREQ
gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
gd->cpu_clk = 50000000UL;
return 50000000;
#endif
}
int board_postclk_init(void)
{
gd->cpu_clk = get_board_sys_clk();
return 0;
}

4
board/compulab/cl-som-imx7/Kconfig
View File

@ -17,10 +17,6 @@ config SYS_USB_DEV
int
default 0
config SYS_MMC_IMG_LOAD_PART
int
default 1
config SYS_USB_IMG_LOAD_PART
int
default 1

41
board/freescale/common/Kconfig
View File

@ -28,36 +28,67 @@ config FSL_USE_PCA9547_MUX
This option enables the PCA9547 I2C mux on Freescale boards.
config VID
depends on DM_I2C
bool "Enable Freescale VID"
depends on I2C || DM_I2C
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
config SPL_VID
bool "Enable Freescale VID in SPL"
depends on I2C || DM_I2C
help
This option enables setting core voltage based on individual
values saved in SoC fuses, in SPL.
if VID || SPL_VID
config VID_FLS_ENV
string "Environment variable for overriding VDD"
help
This option allows for specifying the environment variable
to check to override VDD information.
config VOL_MONITOR_INA220
bool "Enable the INA220 voltage monitor read"
help
This option enables INA220 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_READ
bool "Enable the IR36021 voltage monitor read"
help
This option enables IR36021 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_SET
bool "Enable the IR36021 voltage monitor set"
help
This option enables IR36021 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
help
This option enables LTC3882 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
help
This option enables LTC3882 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
depends on VID
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
depends on VID
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.
endif

2
board/freescale/common/Makefile
View File

@ -33,7 +33,7 @@ obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
endif
obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
obj-$(CONFIG_VID) += vid.o
obj-$(CONFIG_$(SPL_)VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD

4
board/freescale/common/cadmus.c
View File

@ -5,7 +5,7 @@
#include <common.h>
#include <clock_legacy.h>
/*
* CADMUS Board System Registers
@ -37,7 +37,7 @@ get_board_version(void)
unsigned long
get_clock_freq(void)
get_board_sys_clk(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;

2
board/freescale/common/cadmus.h
View File

@ -19,7 +19,7 @@ extern unsigned int get_board_version(void);
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
extern unsigned long get_clock_freq(void);
extern unsigned long get_board_sys_clk(void);
/*

3
board/freescale/common/ics307_clk.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
@ -137,6 +138,7 @@ unsigned long get_board_sys_clk(void)
in_8(&fpga_reg->sclk[2]));
}
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
@ -144,3 +146,4 @@ unsigned long get_board_ddr_clk(void)
in_8(&fpga_reg->dclk[1]),
in_8(&fpga_reg->dclk[2]));
}
#endif

2
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -102,6 +102,7 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@ -126,6 +127,7 @@ unsigned long get_board_sys_clk(void)
}
return 66666666;
}
#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)

1
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>

1
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>

5
board/freescale/ls1088a/ls1088a.c
View File

@ -3,6 +3,7 @@
* Copyright 2017-2018 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
@ -374,6 +375,7 @@ bool if_board_diff_clk(void)
#endif
}
#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@ -397,7 +399,9 @@ unsigned long get_board_sys_clk(void)
return 66666666;
}
#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
@ -415,6 +419,7 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
#endif
#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)

1
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -3,6 +3,7 @@
* Copyright 2015 Freescale Semiconductor
*/
#include <common.h>
#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>

1
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -4,6 +4,7 @@
* Copyright 2017 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>

2
board/freescale/p1010rdb/spl.c
View File

@ -43,7 +43,7 @@ void board_init_f(ulong bootflag)
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);

3
board/freescale/p1010rdb/spl_minimal.c
View File

@ -3,6 +3,7 @@
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <mpc85xx.h>
#include <asm/io.h>
@ -29,7 +30,7 @@ void board_init_f(ulong bootflag)
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);

2
board/freescale/p1_p2_rdb_pc/spl.c
View File

@ -48,7 +48,7 @@ void board_init_f(ulong bootflag)
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
bus_clk = get_board_sys_clk() * plat_ratio;
gd->bus_clk = bus_clk;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,

3
board/freescale/p1_p2_rdb_pc/spl_minimal.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
@ -28,7 +29,7 @@ void board_init_f(ulong bootflag)
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);

3
board/freescale/p2041rdb/p2041rdb.c
View File

@ -4,6 +4,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
@ -148,7 +149,7 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(unsigned long dummy)
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = CPLD_READ(sysclk_sw1);

5
board/freescale/t102xrdb/spl.c
View File

@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)

5
board/freescale/t102xrdb/t102xrdb.c
View File

@ -162,11 +162,6 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{

5
board/freescale/t104xrdb/spl.c
View File

@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{

1
board/freescale/t208xqds/t208xqds.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>

5
board/freescale/t208xrdb/spl.c
View File

@ -24,11 +24,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;

5
board/freescale/t208xrdb/t208xrdb.c
View File

@ -109,11 +109,6 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
int misc_init_r(void)
{
u8 reg;

5
board/freescale/t4rdb/spl.c
View File

@ -30,11 +30,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;

5
board/keymile/kmcent2/kmcent2.c
View File

@ -181,11 +181,6 @@ unsigned long get_serial_clock(unsigned long dummy)
return (gd->bus_clk / 2);
}
unsigned long get_board_sys_clk(unsigned long dummy)
{
return 66666666;
}
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */

2
board/liebherr/display5/spl.c
View File

@ -327,8 +327,10 @@ void board_init_f(ulong dummy)
displ5_set_iomux_misc_spl();
/* Initialize and reset WDT in SPL */
#ifdef CONFIG_SPL_WATCHDOG
hw_watchdog_init();
WATCHDOG_RESET();
#endif
/* load/boot image from boot device */
board_init_r(NULL, 0);

3
board/renesas/eagle/eagle.c
View File

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
@ -50,7 +51,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}

3
board/renesas/gose/gose.c
View File

@ -6,6 +6,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
@ -45,7 +46,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */

3
board/renesas/koelsch/koelsch.c
View File

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
@ -47,7 +48,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */

3
board/renesas/lager/lager.c
View File

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <env_internal.h>
@ -50,7 +51,7 @@ void s_init(void)
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);

3
board/renesas/porter/porter.c
View File

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
@ -47,7 +48,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */

3
board/renesas/stout/stout.c
View File

@ -9,6 +9,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
@ -50,7 +51,7 @@ void s_init(void)
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);

1
board/siemens/capricorn/MAINTAINERS
View File

@ -5,7 +5,6 @@ F: board/siemens/capricorn/
F: include/configs/capricorn-common.h
F: include/configs/deneb.h
F: include/configs/giedi.h
F: include/configs/siemens-ccp-common.h
F: include/configs/siemens-env-common.h
F: configs/deneb_defconfig
F: configs/giedi_defconfig

2
board/socrates/socrates.c
View File

@ -57,7 +57,7 @@ int checkboard (void)
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
f = CONFIG_SYS_CLK_FREQ;
f = get_board_sys_clk();
} else {
src = "PCI_CLK";
f = CONFIG_PCI_CLK_FREQ;

3
board/sunxi/board.c
View File

@ -11,6 +11,7 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <dm.h>
#include <env.h>
#include <hang.h>
@ -667,7 +668,7 @@ void sunxi_board_init(void)
* assured it's being powered with suitable core voltage
*/
if (!power_failed)
clock_set_pll1(CONFIG_SYS_CLK_FREQ);
clock_set_pll1(get_board_sys_clk());
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}

6
board/warp7/Kconfig
View File

@ -14,12 +14,6 @@ config WARP7_ROOT_PART
partition that is typically specified with root=/dev/sdaX or
which gets converted into a root=PARTUUID=some_uuid.
config SYS_FDT_ADDR
hex "FDT load address"
default 0x83000000
help
The address the FDT file should be loaded to.
config IMX_CONFIG
default "board/warp7/imximage.cfg"

3
board/xen/xenguest_arm64/Kconfig
View File

@ -9,4 +9,7 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "xenguest_arm64"
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default SYS_LOAD_ADDR
endif

1
board/xes/common/Makefile
View File

@ -3,7 +3,6 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o

7
board/xes/common/fsl_8xxx_clk.c
View File

@ -4,12 +4,13 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/io.h>
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
unsigned long get_board_sys_clk(ulong dummy)
unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -33,13 +34,13 @@ unsigned long get_board_sys_clk(ulong dummy)
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
unsigned long get_board_ddr_clk(ulong dummy)
unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)

22
board/xes/common/fsl_8xxx_pci.c
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_pci_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */

31
boot/Kconfig
View File

@ -358,11 +358,27 @@ config SYS_TEXT_BASE
help
The address in memory that U-Boot will be running from, initially.
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
config DYNAMIC_SYS_CLK_FREQ
bool "Determine CPU clock frequency at run-time"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
Implement a get_board_sys_clk function that will determine the CPU
clock frequency at run time, rather than define it statically.
config SYS_CLK_FREQ
depends on !DYNAMIC_SYS_CLK_FREQ
int "CPU clock frequency"
default 125000000 if ARCH_LS1012A
default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
default 66660000 if ARCH_T2080
default 33333333 if RCAR_GEN3
default 24000000 if ARCH_EXYNOS
default 20000000 if RCAR_GEN2
default 0
help
A static value for the CPU frequency. Note that if not required
for a given SoC, this can be left at 0.
config ARCH_FIXUP_FDT_MEMORY
bool "Enable arch_fixup_memory_banks() call"
@ -762,6 +778,13 @@ config SD_BOOT
booted via SD/EMMC. This is not a must, some SoCs need this,
some not.
config SD_BOOT_QSPI
bool "Support for booting from SD/EMMC and enable QSPI"
help
Enabling this will make a U-Boot binary that is capable of being
booted via SD/EMMC while enabling QSPI on the platform as well. This
is not a must, some SoCs need this, some not.
config SPI_BOOT
bool "Support for booting from SPI flash"
help

23
cmd/Kconfig
View File

@ -741,7 +741,7 @@ endif
config SYS_MEMTEST_START
hex "default start address for mtest"
default 0
default 0x0
help
This is the default start address for mtest for simple read/write
test. If no arguments are given to mtest, default address is used
@ -2219,6 +2219,27 @@ config CMD_JFFS2
provide the ability to load files, list directories and obtain
filesystem information.
config JFFS2_DEV
string "Default device for JFFS2"
depends on CMD_JFFS2
default "nor0"
help
The default device to use with the jffs2 command.
config JFFS2_PART_OFFSET
hex "Default offset within flash to locate the JFFS2 image"
depends on CMD_JFFS2
default 0x0
help
The default offset within flash to locate the JFFS2 image.
config JFFS2_PART_SIZE
hex "Default size of JFFS2 partition"
depends on CMD_JFFS2
default 0xFFFFFFFF
help
The default size of the JFFS2 partition
config CMD_MTDPARTS
bool "MTD partition support"
depends on MTD

12
cmd/jffs2.c
View File

@ -360,11 +360,7 @@ int mtdparts_init(void)
/* id */
id->mtd_id = "single part";
#if defined(CONFIG_JFFS2_DEV)
dev_name = CONFIG_JFFS2_DEV;
#else
dev_name = "nor0";
#endif
if ((mtd_id_parse(dev_name, NULL, &id->type, &id->num) != 0) ||
(mtd_device_validate(id->type, id->num, &size) != 0)) {
@ -382,17 +378,9 @@ int mtdparts_init(void)
part->name = "static";
part->auto_name = 0;
#if defined(CONFIG_JFFS2_PART_SIZE)
part->size = CONFIG_JFFS2_PART_SIZE;
#else
part->size = SIZE_REMAINING;
#endif
#if defined(CONFIG_JFFS2_PART_OFFSET)
part->offset = CONFIG_JFFS2_PART_OFFSET;
#else
part->offset = 0x00000000;
#endif
part->dev = current_mtd_dev;
INIT_LIST_HEAD(&part->link);

4
cmd/mvebu/bubt.c
View File

@ -271,8 +271,8 @@ static int spi_burn_image(size_t image_size)
u32 erase_bytes;
/* Probe the SPI bus to get the flash device */
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
CONFIG_ENV_SPI_CS,
flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
CONFIG_SF_DEFAULT_CS,
CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE);
if (!flash) {

9
common/Kconfig
View File

@ -534,6 +534,15 @@ config BOARD_LATE_INIT
So this config enable the late init code with the help of board_late_init
function which should defined on respective boards.
config SYS_FSL_CLK
bool
depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || \
(FSL_ESDHC_IMX && (ARCH_MX5 || ARCH_MX6 || ARCH_MX7))
default y
help
Enable to call get_clocks() in board_init_f() for platforms other
than PowerPC or M68k. This is a legacy option. If not TARGET_BRPPT2
config LAST_STAGE_INIT
bool "Call board-specific as last setup step"
help

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