Merge branch '2021-12-23-make-OF_BOARD-a-boolean' into next
Merge v8 of Simon's series to make CONFIG_OF_BOARD a boolean option.
Quoting him:
With Ilias' efforts we have dropped OF_PRIOR_STAGE and OF_HOSTFILE so
there are only three ways to obtain a devicetree:
- OF_SEPARATE - the normal way, where the devicetree is built and
appended to U-Boot
- OF_EMBED - for development purposes, the devicetree is embedded in
the ELF file (also used for EFI)
- OF_BOARD - the board figures it out on its own
The last one is currently set up so that no devicetree is needed at all
in the U-Boot tree. Most boards do provide one, but some don't. Some
don't even provide instructions on how to boot on the board.
The problems with this approach were covered in another patch[1], since
removed from this series.
In practice, OF_BOARD is not really distinct from OF_SEPARATE. Any board
can obtain its devicetree at runtime, even it is has a devicetree built
in U-Boot. This is because U-Boot may be a second-stage bootloader and its
caller may have a better idea about the hardware available in the machine.
This is the case with a few QEMU boards, for example.
So it makes no sense to have OF_BOARD as a 'choice'. It should be an
option, available with either OF_SEPARATE or OF_EMBED. This would allow
rpi3, for example, to run with the devicetree provided by the prior
bootloader.
This series makes this change, adding various missing devicetree files
(and placeholders) to make the build work.
To make the 'prior stage' side of things more deterministic, a new
OF_HAS_PRIOR_STAGE is added, which cannot be disabled by updated a board's
defconfig. This should help to prevent mistakes.
It also adds a run-time message showing where the devicetree came from,
as well as warnings if the board's expected flow is not being used. This
comes originally from the 'standard passage' series, which depends on
this series.
It also provides a few qemu clean-ups discovered along the way. The
qemu-riscv64_spl problem is fixed.
Please see [2] for discussion on the v6 series.
I put Heinrich's Tested-by tag[3] for the series onto the three devicetree
patches (ARM and RISC-V) that I think it most affects. It isn't possible
to apply a tag to a whole series at present and in any case there are
changes in v7.
This series is available at u-boot-dm/ofb-working
[1] https://patchwork.ozlabs.org/project/uboot/patch/20211207001209.3467163-2-sjg@chromium.org/
[2] https://lore.kernel.org/u-boot/20211205133207.GW1220664@bill-the-cat/T/#mcd8c0258827fbc1bb3000b7ff9ba0929df1ddcb2
[3] https://lore.kernel.org/u-boot/93913911-4d20-d28f-ee04-739985184c5e@canonical.com/raw
This commit is contained in:
Tom Rini
commit
bc0abd80b3
16
Makefile
16
Makefile
@ -944,8 +944,9 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
|
||||
endif
|
||||
endif
|
||||
INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
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||||
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
|
||||
INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
|
||||
|
||||
# Allow omitting the .dtb output if it is not normally used
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||||
INPUTS-$(CONFIG_OF_SEPARATE) += $(if $(CONFIG_OF_OMIT_DTB),dts/dt.dtb,u-boot.dtb)
|
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ifeq ($(CONFIG_SPL_FRAMEWORK),y)
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||||
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
|
||||
endif
|
||||
@ -1054,6 +1055,10 @@ quiet_cmd_cfgcheck = CFGCHK $2
|
||||
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
|
||||
$(srctree)/scripts/config_whitelist.txt $(srctree)
|
||||
|
||||
quiet_cmd_ofcheck = OFCHK $2
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cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
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$(srctree)/scripts/of_allowlist.txt
|
||||
|
||||
# Concat the value of all the CONFIGs (result is 'y' or 'yy', etc. )
|
||||
got = $(foreach cfg,$(1),$($(cfg)))
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|
||||
@ -1128,6 +1133,9 @@ endif
|
||||
@# know about unless they are in Kconfig. All the existing CONFIG
|
||||
@# options are whitelisted, so new ones should not be added.
|
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$(call cmd,cfgcheck,u-boot.cfg)
|
||||
@# Check that this build does not override OF_HAS_PRIOR_STAGE by
|
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@# disabling OF_BOARD.
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$(call cmd,ofcheck,$(KCONFIG_CONFIG))
|
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|
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PHONY += dtbs
|
||||
dtbs: dts/dt.dtb
|
||||
@ -1181,7 +1189,7 @@ u-boot.bin: u-boot-fit-dtb.bin FORCE
|
||||
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
|
||||
$(call if_changed,cat)
|
||||
|
||||
else ifeq ($(CONFIG_OF_SEPARATE),y)
|
||||
else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
|
||||
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
|
||||
$(call if_changed,cat)
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||||
|
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@ -1415,7 +1423,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE
|
||||
|
||||
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
|
||||
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
|
||||
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
|
||||
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
|
||||
,$(UBOOT_BIN)) FORCE
|
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$(call if_changed,mkimage)
|
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$(BOARD_SIZE_CHECK)
|
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|
||||
29
README
29
README
@ -646,35 +646,6 @@ The following options need to be configured:
|
||||
which adds regex support to some commands, as for
|
||||
example "env grep" and "setexpr".
|
||||
|
||||
- Device tree:
|
||||
CONFIG_OF_CONTROL
|
||||
If this variable is defined, U-Boot will use a device tree
|
||||
to configure its devices, instead of relying on statically
|
||||
compiled #defines in the board file. This option is
|
||||
experimental and only available on a few boards. The device
|
||||
tree is available in the global data as gd->fdt_blob.
|
||||
|
||||
U-Boot needs to get its device tree from somewhere. This can
|
||||
be done using one of the three options below:
|
||||
|
||||
CONFIG_OF_SEPARATE
|
||||
If this variable is defined, U-Boot will build a device tree
|
||||
binary. It will be called u-boot.dtb. Architecture-specific
|
||||
code will locate it at run-time. Generally this works by:
|
||||
|
||||
cat u-boot.bin u-boot.dtb >image.bin
|
||||
|
||||
and in fact, U-Boot does this for you, creating a file called
|
||||
u-boot-dtb.bin which is useful in the common case. You can
|
||||
still use the individual files if you need something more
|
||||
exotic.
|
||||
|
||||
CONFIG_OF_BOARD
|
||||
If this variable is defined, U-Boot will use the device tree
|
||||
provided by the board at runtime instead of embedding one with
|
||||
the image. Only boards defining board_fdt_blob_setup() support
|
||||
this option (see include/fdtdec.h file).
|
||||
|
||||
- Watchdog:
|
||||
CONFIG_WATCHDOG
|
||||
If this variable is defined, it enables watchdog
|
||||
|
||||
@ -635,6 +635,7 @@ config ARCH_BCMSTB
|
||||
select GPIO_EXTRA_HEADER
|
||||
select OF_CONTROL
|
||||
imply CMD_DM
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
help
|
||||
This enables support for Broadcom ARM-based set-top box
|
||||
chipsets, including the 7445 family of chips.
|
||||
@ -707,12 +708,12 @@ config ARCH_HIGHBANK
|
||||
select DM
|
||||
select DM_SERIAL
|
||||
select OF_CONTROL
|
||||
select OF_BOARD
|
||||
select CLK
|
||||
select CLK_CCF
|
||||
select AHCI
|
||||
select DM_ETH
|
||||
select PHYS_64BIT
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config ARCH_INTEGRATOR
|
||||
bool "ARM Ltd. Integrator family"
|
||||
@ -935,13 +936,13 @@ config ARCH_APPLE
|
||||
select IOMMU
|
||||
select LINUX_KERNEL_IMAGE_HEADER
|
||||
select OF_CONTROL
|
||||
select OF_BOARD
|
||||
select PINCTRL
|
||||
select POSITION_INDEPENDENT
|
||||
select USB
|
||||
imply CMD_DM
|
||||
imply CMD_GPT
|
||||
imply DISTRO_DEFAULTS
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config ARCH_OWL
|
||||
bool "Actions Semi OWL SoCs"
|
||||
@ -966,6 +967,7 @@ config ARCH_QEMU
|
||||
imply DM_RNG
|
||||
imply DM_RTC
|
||||
imply RTC_PL031
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config ARCH_RMOBILE
|
||||
bool "Renesas ARM SoCs"
|
||||
@ -1243,7 +1245,6 @@ config TARGET_VEXPRESS64_JUNO
|
||||
select PL01X_SERIAL
|
||||
select DM
|
||||
select OF_CONTROL
|
||||
select OF_BOARD
|
||||
select CLK
|
||||
select DM_SERIAL
|
||||
select ARM_PSCI_FW
|
||||
@ -1251,6 +1252,7 @@ config TARGET_VEXPRESS64_JUNO
|
||||
select DM_ETH
|
||||
select BLK
|
||||
select USB
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config TARGET_TOTAL_COMPUTE
|
||||
bool "Support Total Compute Platform"
|
||||
@ -1907,6 +1909,7 @@ config ARCH_OCTEONTX
|
||||
select OF_LIVE
|
||||
select BOARD_LATE_INIT
|
||||
select SYS_CACHE_SHIFT_7
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config ARCH_OCTEONTX2
|
||||
bool "Support OcteonTX2 SoCs"
|
||||
@ -1918,6 +1921,7 @@ config ARCH_OCTEONTX2
|
||||
select OF_LIVE
|
||||
select BOARD_LATE_INIT
|
||||
select SYS_CACHE_SHIFT_7
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config TARGET_THUNDERX_88XX
|
||||
bool "Support ThunderX 88xx"
|
||||
@ -1954,6 +1958,8 @@ config TARGET_XENGUEST_ARM64
|
||||
select LINUX_KERNEL_IMAGE_HEADER
|
||||
select XEN_SERIAL
|
||||
select SSCANF
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
endchoice
|
||||
|
||||
config SUPPORT_PASSING_ATAGS
|
||||
|
||||
@ -360,7 +360,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
|
||||
dtb-$(CONFIG_ARCH_VERSAL) += \
|
||||
versal-mini.dtb \
|
||||
versal-mini-emmc0.dtb \
|
||||
versal-mini-emmc1.dtb
|
||||
versal-mini-emmc1.dtb \
|
||||
xilinx-versal-virt.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
|
||||
zynqmp-r5.dtb
|
||||
dtb-$(CONFIG_AM33XX) += \
|
||||
@ -870,6 +871,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
|
||||
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
|
||||
imx7ulp-evk.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_IMX8) += \
|
||||
fsl-imx8qm-apalis.dtb \
|
||||
fsl-imx8qm-mek.dtb \
|
||||
@ -1077,7 +1080,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
|
||||
bcm2837-rpi-3-a-plus.dtb \
|
||||
bcm2837-rpi-3-b.dtb \
|
||||
bcm2837-rpi-3-b-plus.dtb \
|
||||
bcm2837-rpi-cm3-io3.dtb
|
||||
bcm2837-rpi-cm3-io3.dtb \
|
||||
bcm2711-rpi-4-b.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM63158) += \
|
||||
bcm963158.dtb
|
||||
@ -1090,6 +1094,8 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
|
||||
|
||||
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
|
||||
|
||||
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
|
||||
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
|
||||
|
||||
@ -1139,6 +1145,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
||||
mt8516-pumpkin.dtb \
|
||||
mt8518-ap1-emmc.dtb
|
||||
|
||||
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
|
||||
dtb-$(CONFIG_ARCH_OCTEONTX2) += octeontx.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_GE_BX50V3) += \
|
||||
imx6q-bx50v3.dtb \
|
||||
imx6q-b850v3.dtb \
|
||||
@ -1148,7 +1159,10 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
|
||||
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
|
||||
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
|
||||
|
||||
# TODO(Linus Walleij <linus.walleij@linaro.org>): Should us a single vexpress
|
||||
# Kconfig option to build all of these. See examples above.
|
||||
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
|
||||
dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
|
||||
|
||||
@ -1162,6 +1176,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
# Add any required device tree compiler flags here
|
||||
|
||||
262
arch/arm/dts/bcm2711-rpi-4-b.dts
Normal file
262
arch/arm/dts/bcm2711-rpi-4-b.dts
Normal file
@ -0,0 +1,262 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/dts-v1/;
|
||||
#include "bcm2711.dtsi"
|
||||
#include "bcm2711-rpi.dtsi"
|
||||
#include "bcm283x-rpi-usb-peripheral.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
|
||||
model = "Raspberry Pi 4 Model B";
|
||||
|
||||
chosen {
|
||||
/* 8250 auxiliary UART instead of pl011 */
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
led-act {
|
||||
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
|
||||
wifi_pwrseq: wifi-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sd_io_1v8_reg: sd_io_1v8_reg {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vdd-sd-io";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-settling-time-us = <5000>;
|
||||
gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1>,
|
||||
<3300000 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sd_vcc_reg: sd_vcc_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc-sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&ddc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ddc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&expgpio {
|
||||
gpio-line-names = "BT_ON",
|
||||
"WL_ON",
|
||||
"PWR_LED_OFF",
|
||||
"GLOBAL_RESET",
|
||||
"VDD_SD_IO_SEL",
|
||||
"CAM_GPIO",
|
||||
"SD_PWR_ON",
|
||||
"";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/*
|
||||
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
|
||||
* the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
gpio-line-names = "ID_SDA",
|
||||
"ID_SCL",
|
||||
"SDA1",
|
||||
"SCL1",
|
||||
"GPIO_GCLK",
|
||||
"GPIO5",
|
||||
"GPIO6",
|
||||
"SPI_CE1_N",
|
||||
"SPI_CE0_N",
|
||||
"SPI_MISO",
|
||||
"SPI_MOSI",
|
||||
"SPI_SCLK",
|
||||
"GPIO12",
|
||||
"GPIO13",
|
||||
/* Serial port */
|
||||
"TXD1",
|
||||
"RXD1",
|
||||
"GPIO16",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"GPIO19",
|
||||
"GPIO20",
|
||||
"GPIO21",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"GPIO26",
|
||||
"GPIO27",
|
||||
"RGMII_MDIO",
|
||||
"RGMIO_MDC",
|
||||
/* Used by BT module */
|
||||
"CTS0",
|
||||
"RTS0",
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
/* Used by Wifi */
|
||||
"SD1_CLK",
|
||||
"SD1_CMD",
|
||||
"SD1_DATA0",
|
||||
"SD1_DATA1",
|
||||
"SD1_DATA2",
|
||||
"SD1_DATA3",
|
||||
/* Shared with SPI flash */
|
||||
"PWM0_MISO",
|
||||
"PWM1_MOSI",
|
||||
"STATUS_LED_G_CLK",
|
||||
"SPIFLASH_CE_N",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"RGMII_RXCLK",
|
||||
"RGMII_RXCTL",
|
||||
"RGMII_RXD0",
|
||||
"RGMII_RXD1",
|
||||
"RGMII_RXD2",
|
||||
"RGMII_RXD3",
|
||||
"RGMII_TXCLK",
|
||||
"RGMII_TXCTL",
|
||||
"RGMII_TXD0",
|
||||
"RGMII_TXD1",
|
||||
"RGMII_TXD2",
|
||||
"RGMII_TXD3";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pixelvalve0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pixelvalve1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pixelvalve2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pixelvalve4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SDHCI is used to control the SDIO for wireless */
|
||||
&sdhci {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_gpio34>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
status = "okay";
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
/* EMMC2 is used to drive the SD card */
|
||||
&emmc2 {
|
||||
vqmmc-supply = <&sd_io_1v8_reg>;
|
||||
vmmc-supply = <&sd_vcc_reg>;
|
||||
broken-cd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&genet {
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-rxid";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&genet_mdio {
|
||||
phy1: ethernet-phy@1 {
|
||||
/* No PHY interrupt */
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pci@0,0 {
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
reg = <0 0 0 0 0>;
|
||||
|
||||
usb@0,0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* uart0 communicates with the BT module */
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <2000000>;
|
||||
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* uart1 is mapped to the pin header */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_gpio14>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vc4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vec {
|
||||
status = "disabled";
|
||||
};
|
||||
74
arch/arm/dts/bcm2711-rpi.dtsi
Normal file
74
arch/arm/dts/bcm2711-rpi.dtsi
Normal file
@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "bcm2835-rpi.dtsi"
|
||||
|
||||
#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
|
||||
|
||||
/ {
|
||||
/* Will be filled by the bootloader */
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
emmc2bus = &emmc2bus;
|
||||
ethernet0 = &genet;
|
||||
pcie0 = &pcie0;
|
||||
blconfig = &blconfig;
|
||||
};
|
||||
};
|
||||
|
||||
&firmware {
|
||||
firmware_clocks: clocks {
|
||||
compatible = "raspberrypi,firmware-clocks";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
expgpio: gpio {
|
||||
compatible = "raspberrypi,firmware-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reset: reset {
|
||||
compatible = "raspberrypi,firmware-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
|
||||
clock-names = "hdmi", "bvb", "audio", "cec";
|
||||
wifi-2.4ghz-coexistence;
|
||||
};
|
||||
|
||||
&hdmi1 {
|
||||
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
|
||||
clock-names = "hdmi", "bvb", "audio", "cec";
|
||||
wifi-2.4ghz-coexistence;
|
||||
};
|
||||
|
||||
&hvs {
|
||||
clocks = <&firmware_clocks 4>;
|
||||
};
|
||||
|
||||
&rmem {
|
||||
/*
|
||||
* RPi4's co-processor will copy the board's bootloader configuration
|
||||
* into memory for the OS to consume. It'll also update this node with
|
||||
* its placement information.
|
||||
*/
|
||||
blconfig: nvram@0 {
|
||||
compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x0>;
|
||||
no-map;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&vchiq {
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
1100
arch/arm/dts/bcm2711.dtsi
Normal file
1100
arch/arm/dts/bcm2711.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
207
arch/arm/dts/bcm2835-common.dtsi
Normal file
207
arch/arm/dts/bcm2835-common.dtsi
Normal file
@ -0,0 +1,207 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/* This include file covers the common peripherals and configuration between
|
||||
* bcm2835, bcm2836 and bcm2837 implementations.
|
||||
*/
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
soc {
|
||||
dma: dma@7e007000 {
|
||||
compatible = "brcm,bcm2835-dma";
|
||||
reg = <0x7e007000 0xf00>;
|
||||
interrupts = <1 16>,
|
||||
<1 17>,
|
||||
<1 18>,
|
||||
<1 19>,
|
||||
<1 20>,
|
||||
<1 21>,
|
||||
<1 22>,
|
||||
<1 23>,
|
||||
<1 24>,
|
||||
<1 25>,
|
||||
<1 26>,
|
||||
/* dma channel 11-14 share one irq */
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
/* unused shared irq for all channels */
|
||||
<1 28>;
|
||||
interrupt-names = "dma0",
|
||||
"dma1",
|
||||
"dma2",
|
||||
"dma3",
|
||||
"dma4",
|
||||
"dma5",
|
||||
"dma6",
|
||||
"dma7",
|
||||
"dma8",
|
||||
"dma9",
|
||||
"dma10",
|
||||
"dma11",
|
||||
"dma12",
|
||||
"dma13",
|
||||
"dma14",
|
||||
"dma-shared-all";
|
||||
#dma-cells = <1>;
|
||||
brcm,dma-channel-mask = <0x7f35>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@7e00b200 {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pm: watchdog@7e100000 {
|
||||
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x7e100000 0x114>,
|
||||
<0x7e00a000 0x24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_V3D>,
|
||||
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
|
||||
<&clocks BCM2835_CLOCK_H264>,
|
||||
<&clocks BCM2835_CLOCK_ISP>;
|
||||
clock-names = "v3d", "peri_image", "h264", "isp";
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
rng@7e104000 {
|
||||
compatible = "brcm,bcm2835-rng";
|
||||
reg = <0x7e104000 0x10>;
|
||||
interrupts = <2 29>;
|
||||
};
|
||||
|
||||
pixelvalve@7e206000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve0";
|
||||
reg = <0x7e206000 0x100>;
|
||||
interrupts = <2 13>; /* pwa0 */
|
||||
};
|
||||
|
||||
pixelvalve@7e207000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve1";
|
||||
reg = <0x7e207000 0x100>;
|
||||
interrupts = <2 14>; /* pwa1 */
|
||||
};
|
||||
|
||||
thermal: thermal@7e212000 {
|
||||
compatible = "brcm,bcm2835-thermal";
|
||||
reg = <0x7e212000 0x8>;
|
||||
clocks = <&clocks BCM2835_CLOCK_TSENS>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@7e805000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e805000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vec: vec@7e806000 {
|
||||
compatible = "brcm,bcm2835-vec";
|
||||
reg = <0x7e806000 0x1000>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VEC>;
|
||||
interrupts = <2 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
reg = <0x7e807000 0x100>;
|
||||
interrupts = <2 10>; /* pixelvalve */
|
||||
};
|
||||
|
||||
hdmi: hdmi@7e902000 {
|
||||
compatible = "brcm,bcm2835-hdmi";
|
||||
reg = <0x7e902000 0x600>,
|
||||
<0x7e808000 0x100>;
|
||||
interrupts = <2 8>, <2 9>;
|
||||
ddc = <&i2c2>;
|
||||
clocks = <&clocks BCM2835_PLLH_PIX>,
|
||||
<&clocks BCM2835_CLOCK_HSM>;
|
||||
clock-names = "pixel", "hdmi";
|
||||
dmas = <&dma 17>;
|
||||
dma-names = "audio-rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
thermal-sensors = <&thermal>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2c_slave_gpio18: i2c_slave_gpio18 {
|
||||
brcm,pins = <18 19 20 21>;
|
||||
brcm,function = <BCM2835_FSEL_ALT3>;
|
||||
};
|
||||
|
||||
jtag_gpio4: jtag_gpio4 {
|
||||
brcm,pins = <4 5 6 12 13>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
|
||||
pwm0_gpio12: pwm0_gpio12 {
|
||||
brcm,pins = <12>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm0_gpio18: pwm0_gpio18 {
|
||||
brcm,pins = <18>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
pwm0_gpio40: pwm0_gpio40 {
|
||||
brcm,pins = <40>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio13: pwm1_gpio13 {
|
||||
brcm,pins = <13>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio19: pwm1_gpio19 {
|
||||
brcm,pins = <19>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
pwm1_gpio41: pwm1_gpio41 {
|
||||
brcm,pins = <41>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio45: pwm1_gpio45 {
|
||||
brcm,pins = <45>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2s {
|
||||
dmas = <&dma 2>, <&dma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
dmas = <&dma 13>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
|
||||
&spi {
|
||||
dmas = <&dma 6>, <&dma 7>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
@ -8,12 +8,17 @@
|
||||
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model A+";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
@ -99,6 +104,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -107,6 +114,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -8,8 +8,13 @@
|
||||
compatible = "raspberrypi,model-a", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model A";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
@ -94,6 +99,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -102,6 +109,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -9,12 +9,17 @@
|
||||
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B+";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x20000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
@ -101,6 +106,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -109,6 +116,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -9,8 +9,13 @@
|
||||
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B rev2";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
@ -94,6 +99,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -102,6 +109,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -9,8 +9,13 @@
|
||||
compatible = "raspberrypi,model-b", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
@ -89,6 +94,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -97,6 +104,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -79,6 +79,15 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
@ -5,11 +5,16 @@
|
||||
|
||||
/ {
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x20000000>;
|
||||
};
|
||||
|
||||
reg_3v3: fixed-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
|
||||
12
arch/arm/dts/bcm2835-rpi-common.dtsi
Normal file
12
arch/arm/dts/bcm2835-rpi-common.dtsi
Normal file
@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* This include file covers the common peripherals and configuration between
|
||||
* bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's
|
||||
* firmware interface.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/power/raspberrypi-power.h>
|
||||
|
||||
&v3d {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_V3D>;
|
||||
};
|
||||
@ -12,14 +12,19 @@
|
||||
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Zero W";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x20000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
/* 8250 auxiliary UART instead of pl011 */
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -100,12 +105,16 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
|
||||
bus-width = <4>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
@ -116,6 +125,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
|
||||
|
||||
@ -12,8 +12,13 @@
|
||||
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Zero";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x20000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
@ -96,6 +101,15 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
@ -1,15 +1,10 @@
|
||||
#include <dt-bindings/power/raspberrypi-power.h>
|
||||
|
||||
/ {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
act {
|
||||
led-act {
|
||||
label = "ACT";
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "heartbeat";
|
||||
@ -18,8 +13,12 @@
|
||||
|
||||
soc {
|
||||
firmware: firmware {
|
||||
compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
|
||||
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mboxes = <&mailbox>;
|
||||
dma-ranges;
|
||||
};
|
||||
|
||||
power: power {
|
||||
@ -64,32 +63,10 @@
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_gpio48>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_USB>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vec {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_VEC>;
|
||||
status = "okay";
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "bcm283x.dtsi"
|
||||
#include "bcm2835-common.dtsi"
|
||||
#include "bcm2835-rpi-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
@ -10,15 +10,16 @@
|
||||
model = "Raspberry Pi 2 Model B";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
@ -105,6 +106,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
@ -113,6 +116,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio14>;
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "bcm283x.dtsi"
|
||||
#include "bcm2835-common.dtsi"
|
||||
#include "bcm2835-rpi-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2836";
|
||||
|
||||
@ -14,17 +14,20 @@
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x20000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -117,6 +120,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
|
||||
@ -15,17 +15,20 @@
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
led-pwr {
|
||||
label = "PWR";
|
||||
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
|
||||
@ -124,6 +127,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
|
||||
@ -15,11 +15,12 @@
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
act {
|
||||
led-act {
|
||||
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
@ -125,6 +126,8 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* uart0 communicates with the BT module */
|
||||
|
||||
@ -78,6 +78,15 @@
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhost {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhost_gpio48>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
@ -5,9 +5,18 @@
|
||||
|
||||
/ {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
/*
|
||||
* Since there is no upstream GPIO driver yet,
|
||||
* remove the incomplete node.
|
||||
*/
|
||||
/delete-node/ led-act;
|
||||
};
|
||||
|
||||
reg_3v3: fixed-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
|
||||
@ -1,4 +1,6 @@
|
||||
#include "bcm283x.dtsi"
|
||||
#include "bcm2835-common.dtsi"
|
||||
#include "bcm2835-rpi-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2837";
|
||||
|
||||
7
arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi
Normal file
7
arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi
Normal file
@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
&usb {
|
||||
dr_mode = "peripheral";
|
||||
g-rx-fifo-size = <256>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <256 256 512 512 512 768 768>;
|
||||
};
|
||||
@ -18,7 +18,6 @@
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
model = "BCM2835";
|
||||
interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@ -31,16 +30,27 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
rmem: reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x4000000>; /* 64MB */
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&thermal>;
|
||||
|
||||
trips {
|
||||
cpu-crit {
|
||||
temperature = <80000>;
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
@ -56,7 +66,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
timer@7e003000 {
|
||||
system_timer: timer@7e003000 {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
@ -67,74 +77,12 @@
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
txp@7e004000 {
|
||||
txp: txp@7e004000 {
|
||||
compatible = "brcm,bcm2835-txp";
|
||||
reg = <0x7e004000 0x20>;
|
||||
interrupts = <1 11>;
|
||||
};
|
||||
|
||||
dma: dma@7e007000 {
|
||||
compatible = "brcm,bcm2835-dma";
|
||||
reg = <0x7e007000 0xf00>;
|
||||
interrupts = <1 16>,
|
||||
<1 17>,
|
||||
<1 18>,
|
||||
<1 19>,
|
||||
<1 20>,
|
||||
<1 21>,
|
||||
<1 22>,
|
||||
<1 23>,
|
||||
<1 24>,
|
||||
<1 25>,
|
||||
<1 26>,
|
||||
/* dma channel 11-14 share one irq */
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
/* unused shared irq for all channels */
|
||||
<1 28>;
|
||||
interrupt-names = "dma0",
|
||||
"dma1",
|
||||
"dma2",
|
||||
"dma3",
|
||||
"dma4",
|
||||
"dma5",
|
||||
"dma6",
|
||||
"dma7",
|
||||
"dma8",
|
||||
"dma9",
|
||||
"dma10",
|
||||
"dma11",
|
||||
"dma12",
|
||||
"dma13",
|
||||
"dma14",
|
||||
"dma-shared-all";
|
||||
#dma-cells = <1>;
|
||||
brcm,dma-channel-mask = <0x7f35>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@7e00b200 {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pm: watchdog@7e100000 {
|
||||
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x7e100000 0x114>,
|
||||
<0x7e00a000 0x24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_V3D>,
|
||||
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
|
||||
<&clocks BCM2835_CLOCK_H264>,
|
||||
<&clocks BCM2835_CLOCK_ISP>;
|
||||
clock-names = "v3d", "peri_image", "h264", "isp";
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
clocks: cprman@7e101000 {
|
||||
compatible = "brcm,bcm2835-cprman";
|
||||
#clock-cells = <1>;
|
||||
@ -149,12 +97,6 @@
|
||||
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
|
||||
};
|
||||
|
||||
rng@7e104000 {
|
||||
compatible = "brcm,bcm2835-rng";
|
||||
reg = <0x7e104000 0x10>;
|
||||
interrupts = <2 29>;
|
||||
};
|
||||
|
||||
mailbox: mailbox@7e00b880 {
|
||||
compatible = "brcm,bcm2835-mbox";
|
||||
reg = <0x7e00b880 0x40>;
|
||||
@ -184,8 +126,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
/* Defines pin muxing groups according to
|
||||
* BCM2835-ARM-Peripherals.pdf page 102.
|
||||
/* Defines common pin muxing groups
|
||||
*
|
||||
* While each pin can have its mux selected
|
||||
* for various functions individually, some
|
||||
@ -263,15 +204,7 @@
|
||||
brcm,pins = <44 45>;
|
||||
brcm,function = <BCM2835_FSEL_ALT2>;
|
||||
};
|
||||
i2c_slave_gpio18: i2c_slave_gpio18 {
|
||||
brcm,pins = <18 19 20 21>;
|
||||
brcm,function = <BCM2835_FSEL_ALT3>;
|
||||
};
|
||||
|
||||
jtag_gpio4: jtag_gpio4 {
|
||||
brcm,pins = <4 5 6 12 13>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
jtag_gpio22: jtag_gpio22 {
|
||||
brcm,pins = <22 23 24 25 26 27>;
|
||||
brcm,function = <BCM2835_FSEL_ALT4>;
|
||||
@ -286,35 +219,6 @@
|
||||
brcm,function = <BCM2835_FSEL_ALT2>;
|
||||
};
|
||||
|
||||
pwm0_gpio12: pwm0_gpio12 {
|
||||
brcm,pins = <12>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm0_gpio18: pwm0_gpio18 {
|
||||
brcm,pins = <18>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
pwm0_gpio40: pwm0_gpio40 {
|
||||
brcm,pins = <40>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio13: pwm1_gpio13 {
|
||||
brcm,pins = <13>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio19: pwm1_gpio19 {
|
||||
brcm,pins = <19>;
|
||||
brcm,function = <BCM2835_FSEL_ALT5>;
|
||||
};
|
||||
pwm1_gpio41: pwm1_gpio41 {
|
||||
brcm,pins = <41>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
pwm1_gpio45: pwm1_gpio45 {
|
||||
brcm,pins = <45>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
};
|
||||
|
||||
sdhost_gpio48: sdhost_gpio48 {
|
||||
brcm,pins = <48 49 50 51 52 53>;
|
||||
brcm,function = <BCM2835_FSEL_ALT0>;
|
||||
@ -396,8 +300,8 @@
|
||||
};
|
||||
|
||||
uart0: serial@7e201000 {
|
||||
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x1000>;
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x200>;
|
||||
interrupts = <2 25>;
|
||||
clocks = <&clocks BCM2835_CLOCK_UART>,
|
||||
<&clocks BCM2835_CLOCK_VPU>;
|
||||
@ -410,8 +314,6 @@
|
||||
reg = <0x7e202000 0x100>;
|
||||
interrupts = <2 24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
dmas = <&dma 13>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -419,16 +321,12 @@
|
||||
compatible = "brcm,bcm2835-i2s";
|
||||
reg = <0x7e203000 0x24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_PCM>;
|
||||
|
||||
dmas = <&dma 2>,
|
||||
<&dma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@7e204000 {
|
||||
compatible = "brcm,bcm2835-spi";
|
||||
reg = <0x7e204000 0x1000>;
|
||||
reg = <0x7e204000 0x200>;
|
||||
interrupts = <2 22>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
@ -438,7 +336,7 @@
|
||||
|
||||
i2c0: i2c@7e205000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e205000 0x1000>;
|
||||
reg = <0x7e205000 0x200>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
@ -446,18 +344,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pixelvalve@7e206000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve0";
|
||||
reg = <0x7e206000 0x100>;
|
||||
interrupts = <2 13>; /* pwa0 */
|
||||
};
|
||||
|
||||
pixelvalve@7e207000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve1";
|
||||
reg = <0x7e207000 0x100>;
|
||||
interrupts = <2 14>; /* pwa1 */
|
||||
};
|
||||
|
||||
dpi: dpi@7e208000 {
|
||||
compatible = "brcm,bcm2835-dpi";
|
||||
reg = <0x7e208000 0x8c>;
|
||||
@ -486,13 +372,6 @@
|
||||
"dsi0_ddr2",
|
||||
"dsi0_ddr";
|
||||
|
||||
};
|
||||
|
||||
thermal: thermal@7e212000 {
|
||||
compatible = "brcm,bcm2835-thermal";
|
||||
reg = <0x7e212000 0x8>;
|
||||
clocks = <&clocks BCM2835_CLOCK_TSENS>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -541,7 +420,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: sdhci@7e300000 {
|
||||
sdhci: mmc@7e300000 {
|
||||
compatible = "brcm,bcm2835-sdhci";
|
||||
reg = <0x7e300000 0x100>;
|
||||
interrupts = <2 30>;
|
||||
@ -585,44 +464,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@7e805000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e805000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vec: vec@7e806000 {
|
||||
compatible = "brcm,bcm2835-vec";
|
||||
reg = <0x7e806000 0x1000>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VEC>;
|
||||
interrupts = <2 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
reg = <0x7e807000 0x100>;
|
||||
interrupts = <2 10>; /* pixelvalve */
|
||||
};
|
||||
|
||||
hdmi: hdmi@7e902000 {
|
||||
compatible = "brcm,bcm2835-hdmi";
|
||||
reg = <0x7e902000 0x600>,
|
||||
<0x7e808000 0x100>;
|
||||
interrupts = <2 8>, <2 9>;
|
||||
ddc = <&i2c2>;
|
||||
clocks = <&clocks BCM2835_PLLH_PIX>,
|
||||
<&clocks BCM2835_CLOCK_HSM>;
|
||||
clock-names = "pixel", "hdmi";
|
||||
dmas = <&dma 17>;
|
||||
dma-names = "audio-rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@7e980000 {
|
||||
compatible = "brcm,bcm2835-usb";
|
||||
reg = <0x7e980000 0x10000>;
|
||||
@ -634,36 +475,19 @@
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* The oscillator is the root of the clock tree. */
|
||||
clk_osc: clock@3 {
|
||||
clk_osc: clk-osc {
|
||||
compatible = "fixed-clock";
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "osc";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
clk_usb: clock@4 {
|
||||
clk_usb: clk-usb {
|
||||
compatible = "fixed-clock";
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "otg";
|
||||
clock-frequency = <480000000>;
|
||||
|
||||
15
arch/arm/dts/bcm7xxx.dts
Normal file
15
arch/arm/dts/bcm7xxx.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Empty devicetre file for bcm7260 board
|
||||
*
|
||||
* This is required to make the board build with CONFIG OF_SEPARATE
|
||||
* In-tree document explains how to obtain a real devicetree using 'bolt' but
|
||||
* I did not attempt this.
|
||||
*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
9
arch/arm/dts/highbank.dts
Normal file
9
arch/arm/dts/highbank.dts
Normal file
@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Empty devicetree for highbank/midway
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
831
arch/arm/dts/juno-base.dtsi
Normal file
831
arch/arm/dts/juno-base.dtsi
Normal file
@ -0,0 +1,831 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "juno-clocks.dtsi"
|
||||
#include "juno-motherboard.dtsi"
|
||||
|
||||
/ {
|
||||
/*
|
||||
* Devices shared by all Juno boards
|
||||
*/
|
||||
|
||||
memtimer: timer@2a810000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||
clock-frequency = <50000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x2a820000 0x20000>;
|
||||
status = "disabled";
|
||||
frame@2a830000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x10000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
mailbox: mhu@2b1f0000 {
|
||||
compatible = "arm,mhu", "arm,primecell";
|
||||
reg = <0x0 0x2b1f0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&soc_refclk100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smmu_gpu: iommu@2b400000 {
|
||||
compatible = "arm,mmu-400", "arm,smmu-v1";
|
||||
reg = <0x0 0x2b400000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
power-domains = <&scpi_devpd 1>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu_pcie: iommu@2b500000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x2b500000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu_etr: iommu@2b600000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x2b600000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c010000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
reg = <0x0 0x2c010000 0 0x1000>,
|
||||
<0x0 0x2c02f000 0 0x2000>,
|
||||
<0x0 0x2c04f000 0 0x2000>,
|
||||
<0x0 0x2c06f000 0 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
ranges = <0 0 0x2c1c0000 0x40000>;
|
||||
|
||||
v2m_0: v2m@0 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0 0x10000>;
|
||||
};
|
||||
|
||||
v2m@10000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x10000 0x10000>;
|
||||
};
|
||||
|
||||
v2m@20000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x20000 0x10000>;
|
||||
};
|
||||
|
||||
v2m@30000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x30000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Juno TRMs specify the size for these coresight components as 64K.
|
||||
* The actual size is just 4K though 64K is reserved. Access to the
|
||||
* unmapped reserved region results in a DECERR response.
|
||||
*/
|
||||
etf@20010000 { /* etf0 */
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etf0_in_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etf0_out_port: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
|
||||
main_funnel: funnel@20040000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
main_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&etf0_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
main_funnel_in_ports: in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
main_funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&cluster0_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
main_funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@20070000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20070000 0 0x1000>;
|
||||
iommus = <&smmu_etr 0>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
arm,scatter-gather;
|
||||
in-ports {
|
||||
port {
|
||||
etr_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stm@20100000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x20100000 0 0x1000>,
|
||||
<0 0x28000000 0 0x1000000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
stm_out_port: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@20120000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x20120000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etr_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug0: cpu-debug@22010000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x22010000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm0: etm@22040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x22040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster0_etm0_out_port: endpoint {
|
||||
remote-endpoint = <&cluster0_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@220c0000 { /* cluster0 funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x220c0000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster0_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
cluster0_funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&cluster0_etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
cluster0_funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&cluster0_etm1_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug1: cpu-debug@22110000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x22110000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm1: etm@22140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x22140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster0_etm1_out_port: endpoint {
|
||||
remote-endpoint = <&cluster0_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug2: cpu-debug@23010000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23010000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm2: etm@23040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm0_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@230c0000 { /* cluster1 funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x230c0000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
cluster1_funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&cluster1_etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
cluster1_funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&cluster1_etm1_out_port>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
cluster1_funnel_in_port2: endpoint {
|
||||
remote-endpoint = <&cluster1_etm2_out_port>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
cluster1_funnel_in_port3: endpoint {
|
||||
remote-endpoint = <&cluster1_etm3_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug3: cpu-debug@23110000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23110000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm3: etm@23140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm1_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug4: cpu-debug@23210000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23210000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm4: etm@23240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23240000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm2_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug5: cpu-debug@23310000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23310000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm5: etm@23340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23340000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm3_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@2d000000 {
|
||||
compatible = "arm,juno-mali", "arm,mali-t624";
|
||||
reg = <0 0x2d000000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
power-domains = <&scpi_devpd 1>;
|
||||
dma-coherent;
|
||||
/* The SMMU is only really of interest to bare-metal hypervisors */
|
||||
/* iommus = <&smmu_gpu 0>; */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram: sram@2e000000 {
|
||||
compatible = "arm,juno-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0x2e000000 0x0 0x8000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x2e000000 0x8000>;
|
||||
|
||||
cpu_scp_lpri: scp-sram@0 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-sram@200 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie_ctlr: pcie@40000000 {
|
||||
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
|
||||
bus-range = <0 255>;
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
|
||||
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
|
||||
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
|
||||
/* Standard AXI Translation entries as programmed by EDK2 */
|
||||
dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>,
|
||||
<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
|
||||
<0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-parent = <&v2m_0>;
|
||||
status = "disabled";
|
||||
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
|
||||
iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
|
||||
};
|
||||
|
||||
scpi {
|
||||
compatible = "arm,scpi";
|
||||
mboxes = <&mailbox 1>;
|
||||
shmem = <&cpu_scp_hpri>;
|
||||
|
||||
clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: clocks-0 {
|
||||
compatible = "arm,scpi-dvfs-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <0>, <1>, <2>;
|
||||
clock-output-names = "atlclk", "aplclk","gpuclk";
|
||||
};
|
||||
scpi_clk: clocks-1 {
|
||||
compatible = "arm,scpi-variable-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <3>;
|
||||
clock-output-names = "pxlclk";
|
||||
};
|
||||
};
|
||||
|
||||
scpi_devpd: power-controller {
|
||||
compatible = "arm,scpi-power-domains";
|
||||
num-domains = <2>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scpi_sensors0: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
pmic {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 3>;
|
||||
};
|
||||
|
||||
big_cluster_thermal_zone: big-cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
little_cluster_thermal_zone: little-cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu0_thermal_zone: gpu0 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu1_thermal_zone: gpu1 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 24>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
smmu_dma: iommu@7fb00000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
smmu_hdlcd1: iommu@7fb10000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb10000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
};
|
||||
|
||||
smmu_hdlcd0: iommu@7fb20000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
};
|
||||
|
||||
smmu_usb: iommu@7fb30000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb30000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x7ff00000 0 0x1000>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_dma 0>,
|
||||
<&smmu_dma 1>,
|
||||
<&smmu_dma 2>,
|
||||
<&smmu_dma 3>,
|
||||
<&smmu_dma 4>,
|
||||
<&smmu_dma 5>,
|
||||
<&smmu_dma 6>,
|
||||
<&smmu_dma 7>,
|
||||
<&smmu_dma 8>;
|
||||
clocks = <&soc_faxiclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
hdlcd@7ff50000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x7ff50000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_hdlcd1 0>;
|
||||
clocks = <&scpi_clk 3>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
hdlcd1_output: endpoint {
|
||||
remote-endpoint = <&tda998x_1_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdlcd@7ff60000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x7ff60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_hdlcd0 0>;
|
||||
clocks = <&scpi_clk 3>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
hdlcd0_output: endpoint {
|
||||
remote-endpoint = <&tda998x_0_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc_uart0: serial@7ff80000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c@7ffa0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x7ffa0000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <500>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
|
||||
hdmi-transmitter@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
port {
|
||||
tda998x_0_input: endpoint {
|
||||
remote-endpoint = <&hdlcd0_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-transmitter@71 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x71>;
|
||||
port {
|
||||
tda998x_1_input: endpoint {
|
||||
remote-endpoint = <&hdlcd1_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@7ffb0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_usb 0>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
usb@7ffc0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_usb 0>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
||||
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
||||
<0x00000008 0x80000000 0x1 0x80000000>;
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
site2: tlx-bus@60000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x60000000 0x10000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0>;
|
||||
interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
46
arch/arm/dts/juno-clocks.dtsi
Normal file
46
arch/arm/dts/juno-clocks.dtsi
Normal file
@ -0,0 +1,46 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform clocks
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
/ {
|
||||
/* SoC fixed clocks */
|
||||
soc_uartclk: refclk7372800hz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <7372800>;
|
||||
clock-output-names = "juno:uartclk";
|
||||
};
|
||||
|
||||
soc_usb48mhz: clk48mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "clk48mhz";
|
||||
};
|
||||
|
||||
soc_smc50mhz: clk50mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "smc_clk";
|
||||
};
|
||||
|
||||
soc_refclk100mhz: refclk100mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "apb_pclk";
|
||||
};
|
||||
|
||||
soc_faxiclk: refclk400mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <400000000>;
|
||||
clock-output-names = "faxi_clk";
|
||||
};
|
||||
};
|
||||
85
arch/arm/dts/juno-cs-r1r2.dtsi
Normal file
85
arch/arm/dts/juno-cs-r1r2.dtsi
Normal file
@ -0,0 +1,85 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/ {
|
||||
funnel@20130000 { /* cssys1 */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20130000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
csys1_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&etf1_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
port {
|
||||
csys1_funnel_in_port0: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
etf@20140000 { /* etf1 */
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
in-ports {
|
||||
port {
|
||||
etf1_in_port: endpoint {
|
||||
remote-endpoint = <&csys1_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
out-ports {
|
||||
port {
|
||||
etf1_out_port: endpoint {
|
||||
remote-endpoint = <&csys2_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@20150000 { /* cssys2 */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20150000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
csys2_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csys2_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
csys2_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
303
arch/arm/dts/juno-motherboard.dtsi
Normal file
303
arch/arm/dts/juno-motherboard.dtsi
Normal file
@ -0,0 +1,303 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform motherboard peripherals
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
mb_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "juno_mb:clk24mhz";
|
||||
};
|
||||
|
||||
mb_clk25mhz: clk25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "juno_mb:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "juno_mb:refclk32khz";
|
||||
};
|
||||
|
||||
mb_fixed_3v3: mcc-sb-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MCC_SB_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <116>;
|
||||
label = "POWER";
|
||||
gpios = <&iofpga_gpio0 0 0x4>;
|
||||
};
|
||||
home-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <102>;
|
||||
label = "HOME";
|
||||
gpios = <&iofpga_gpio0 1 0x4>;
|
||||
};
|
||||
rlock-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <152>;
|
||||
label = "RLOCK";
|
||||
gpios = <&iofpga_gpio0 2 0x4>;
|
||||
};
|
||||
vol-up-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <115>;
|
||||
label = "VOL+";
|
||||
gpios = <&iofpga_gpio0 3 0x4>;
|
||||
};
|
||||
vol-down-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <114>;
|
||||
label = "VOL-";
|
||||
gpios = <&iofpga_gpio0 4 0x4>;
|
||||
};
|
||||
nmi-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <99>;
|
||||
label = "NMI";
|
||||
gpios = <&iofpga_gpio0 5 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x8000000 0 0x8000000 0x18000000>;
|
||||
|
||||
motherboard-bus@8000000 {
|
||||
compatible = "arm,vexpress,v2p-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
arm,hbi = <0x252>;
|
||||
arm,vexpress,site = <0>;
|
||||
|
||||
flash@0 {
|
||||
/* 2 * 32MiB NOR Flash memory mounted on CS0 */
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
/*
|
||||
* Unfortunately, accessing the flash disturbs
|
||||
* the CPU idle states (suspend) and CPU
|
||||
* hotplug of the platform. For this reason,
|
||||
* flash hardware access is disabled by default.
|
||||
*/
|
||||
status = "disabled";
|
||||
partitions {
|
||||
compatible = "arm,arm-firmware-suite";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@200000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <2 0x00000000 0x10000>;
|
||||
interrupts = <3>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
clocks = <&mb_clk25mhz>;
|
||||
vdd33a-supply = <&mb_fixed_3v3>;
|
||||
vddvario-supply = <&mb_fixed_3v3>;
|
||||
};
|
||||
|
||||
iofpga-bus@300000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
v2m_sysctl: sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
apbregs@10000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x010000 0x1000>;
|
||||
|
||||
led0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "vexpress:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "vexpress:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "vexpress:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "vexpress:3";
|
||||
linux,default-trigger = "cpu1";
|
||||
default-state = "off";
|
||||
};
|
||||
led4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "vexpress:4";
|
||||
linux,default-trigger = "cpu2";
|
||||
default-state = "off";
|
||||
};
|
||||
led5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "vexpress:5";
|
||||
linux,default-trigger = "cpu3";
|
||||
default-state = "off";
|
||||
};
|
||||
led6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "vexpress:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "vexpress:7";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mmc@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <5>;
|
||||
/* cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>; */
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&mb_fixed_3v3>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@60000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@70000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x10000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x10000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
iofpga_gpio0: gpio@1d0000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x1d0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
20
arch/arm/dts/juno-r2-u-boot.dtsi
Normal file
20
arch/arm/dts/juno-r2-u-boot.dtsi
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform additions for U-Boot
|
||||
*/
|
||||
|
||||
/ {
|
||||
bus@8000000 {
|
||||
motherboard-bus@8000000 {
|
||||
/*
|
||||
* This should not be marked "disabled" in U-Boot. The
|
||||
* boot loader is not using some CPU idle states and
|
||||
* hotplug but may be very interested in accessing the
|
||||
* flash.
|
||||
*/
|
||||
flash@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
322
arch/arm/dts/juno-r2.dts
Normal file
322
arch/arm/dts/juno-r2.dts
Normal file
@ -0,0 +1,322 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Ltd. Juno Platform
|
||||
*
|
||||
* Copyright (c) 2015 ARM Ltd.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "juno-base.dtsi"
|
||||
#include "juno-cs-r1r2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Juno development board (r2)";
|
||||
compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &soc_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <400>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A72_0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&A72_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A72_1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&A72_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A72_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu-a72 {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A72_0>,
|
||||
<&A72_1>;
|
||||
};
|
||||
|
||||
pmu-a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>,
|
||||
<&A53_1>,
|
||||
<&A53_2>,
|
||||
<&A53_3>;
|
||||
};
|
||||
};
|
||||
|
||||
&memtimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_ctlr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smmu_pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&etm1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&etm2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&etm3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&etm4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&etm5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&big_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&little_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu0_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu1_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etf0_out_port {
|
||||
remote-endpoint = <&csys2_funnel_in_port0>;
|
||||
};
|
||||
|
||||
&replicator_in_port0 {
|
||||
remote-endpoint = <&csys2_funnel_out_port>;
|
||||
};
|
||||
|
||||
&csys1_funnel_in_port0 {
|
||||
remote-endpoint = <&stm_out_port>;
|
||||
};
|
||||
|
||||
&stm_out_port {
|
||||
remote-endpoint = <&csys1_funnel_in_port0>;
|
||||
};
|
||||
|
||||
&cpu_debug0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&cpu_debug1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&cpu_debug2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&cpu_debug3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&cpu_debug4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&cpu_debug5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
14
arch/arm/dts/octeontx.dts
Normal file
14
arch/arm/dts/octeontx.dts
Normal file
@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Dummy devicetre file for octeontx2 boards
|
||||
*
|
||||
* This is required to make the board build with CONFIG OF_SEPARATE
|
||||
* I could not find any in-tree documentation at all so this is a dummy file.
|
||||
*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
11
arch/arm/dts/qemu-arm.dts
Normal file
11
arch/arm/dts/qemu-arm.dts
Normal file
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Empty device tree for qemu_arm
|
||||
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
11
arch/arm/dts/qemu-arm64.dts
Normal file
11
arch/arm/dts/qemu-arm64.dts
Normal file
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Empty device tree for qemu_arm64
|
||||
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
15
arch/arm/dts/xenguest-arm64.dts
Normal file
15
arch/arm/dts/xenguest-arm64.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Empty devicetree file for xenguest_arm64
|
||||
*
|
||||
* This is required to make the board build with CONFIG OF_SEPARATE
|
||||
* Build instructions at xenguest_arm64.rst are inadequate for obtaining a real
|
||||
* devicetree.
|
||||
*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
11
arch/arm/dts/xilinx-versal-virt.dts
Normal file
11
arch/arm/dts/xilinx-versal-virt.dts
Normal file
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Empty device tree for versal-virt board
|
||||
*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
@ -163,6 +163,7 @@ config TARGET_RPI_4_32B
|
||||
|
||||
This option creates a build targeting the ARMv7/AArch32 ISA.
|
||||
select BCM2711_32B
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config TARGET_RPI_4
|
||||
bool "Raspberry Pi 4 64-bit build"
|
||||
@ -188,6 +189,7 @@ config TARGET_RPI_4
|
||||
|
||||
This option creates a build targeting the ARMv8/AArch64 ISA.
|
||||
select BCM2711_64B
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config TARGET_RPI_ARM64
|
||||
bool "Raspberry Pi one binary 64-bit build"
|
||||
@ -195,6 +197,7 @@ config TARGET_RPI_ARM64
|
||||
Support for all armv8 based Raspberry Pi variants, such as
|
||||
the RPi 4 model B, in AArch64 (64-bit) mode.
|
||||
select ARM64
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
endchoice
|
||||
|
||||
|
||||
@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500
|
||||
bool "Support qemu-ppce500"
|
||||
select ARCH_QEMU_E500
|
||||
select PHYS_64BIT
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
config TARGET_T1024RDB
|
||||
bool "Support T1024RDB"
|
||||
|
||||
@ -18,6 +18,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
|
||||
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
|
||||
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
|
||||
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
|
||||
dtb-$(CONFIG_TARGET_QEMU_PPCE500) += qemu-ppce500.dtb
|
||||
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
|
||||
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
|
||||
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
|
||||
|
||||
10
arch/powerpc/dts/qemu-ppce500.dts
Normal file
10
arch/powerpc/dts/qemu-ppce500.dts
Normal file
@ -0,0 +1,10 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Empty device tree for qemu-ppce400
|
||||
*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
};
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
|
||||
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
|
||||
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
|
||||
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
|
||||
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
|
||||
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
|
||||
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
|
||||
|
||||
@ -6,3 +6,6 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "binman.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
11
arch/riscv/dts/qemu-virt64.dts
Normal file
11
arch/riscv/dts/qemu-virt64.dts
Normal file
@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "binman.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
@ -65,5 +65,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
imply VIRTIO_BLK
|
||||
imply MTD_NOR_FLASH
|
||||
imply CFI_FLASH
|
||||
imply OF_HAS_PRIOR_STAGE
|
||||
|
||||
endif
|
||||
|
||||
@ -128,6 +128,8 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
|
||||
lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
|
||||
lmb_dump_all_force(&lmb);
|
||||
if (IS_ENABLED(CONFIG_OF_REAL))
|
||||
printf("devicetree = %s\n", fdtdec_get_srcname());
|
||||
}
|
||||
|
||||
arch_print_bdinfo();
|
||||
|
||||
@ -586,6 +586,29 @@ int initr_mem(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
static int dm_announce(void)
|
||||
{
|
||||
int device_count;
|
||||
int uclass_count;
|
||||
|
||||
if (IS_ENABLED(CONFIG_DM)) {
|
||||
dm_get_stats(&device_count, &uclass_count);
|
||||
printf("Core: %d devices, %d uclasses", device_count,
|
||||
uclass_count);
|
||||
if (CONFIG_IS_ENABLED(OF_REAL))
|
||||
printf(", devicetree: %s", fdtdec_get_srcname());
|
||||
printf("\n");
|
||||
if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) &&
|
||||
(gd->fdt_src == FDTSRC_SEPARATE ||
|
||||
gd->fdt_src == FDTSRC_EMBED)) {
|
||||
printf("Warning: Unexpected devicetree source (not from a prior stage)");
|
||||
printf("Warning: U-Boot may not function properly\n");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int run_main_loop(void)
|
||||
{
|
||||
#ifdef CONFIG_SANDBOX
|
||||
@ -661,6 +684,7 @@ static init_fnc_t init_sequence_r[] = {
|
||||
stdio_init_tables,
|
||||
serial_initialize,
|
||||
initr_announce,
|
||||
dm_announce,
|
||||
#if CONFIG_IS_ENABLED(WDT)
|
||||
initr_watchdog,
|
||||
#endif
|
||||
|
||||
@ -17,7 +17,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@ -21,7 +21,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
|
||||
@ -23,7 +23,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
|
||||
@ -18,7 +18,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@ -22,7 +22,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
|
||||
@ -24,7 +24,6 @@ CONFIG_CMD_SF_TEST=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
|
||||
@ -7,6 +7,7 @@ CONFIG_TARGET_BCM7260=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x814800
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx"
|
||||
CONFIG_ENV_OFFSET_REDUND=0x824800
|
||||
CONFIG_SYS_LOAD_ADDR=0x02000000
|
||||
CONFIG_FIT=y
|
||||
@ -26,7 +27,6 @@ CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
|
||||
@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x1E0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx"
|
||||
CONFIG_ENV_OFFSET_REDUND=0x1F0000
|
||||
CONFIG_SYS_LOAD_ADDR=0x02000000
|
||||
CONFIG_FIT=y
|
||||
@ -27,7 +28,6 @@ CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
|
||||
@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000
|
||||
CONFIG_SYS_MALLOC_LEN=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="highbank"
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
|
||||
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -21,7 +22,6 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_IS_IN_NVRAM=y
|
||||
CONFIG_ENV_ADDR=0xFFF88000
|
||||
CONFIG_SCSI_AHCI=y
|
||||
|
||||
@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_TARGET_OCTEONTX2_95XX=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
|
||||
CONFIG_DEBUG_UART_BASE=0x87e028000000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
@ -63,7 +64,6 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
|
||||
@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_TARGET_OCTEONTX2_96XX=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
|
||||
CONFIG_DEBUG_UART_BASE=0x87e028000000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
@ -64,7 +65,6 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
|
||||
@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_TARGET_OCTEONTX_81XX=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
|
||||
CONFIG_DEBUG_UART_BASE=0x87e028000000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
@ -65,7 +66,6 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
|
||||
@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_TARGET_OCTEONTX_83XX=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="octeontx"
|
||||
CONFIG_DEBUG_UART_BASE=0x87e028000000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
@ -62,7 +63,6 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xf01000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_QEMU_PPCE500=y
|
||||
@ -26,7 +27,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
@ -55,4 +55,5 @@ CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_ADDR_MAP=y
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
CONFIG_PANIC_HANG=y
|
||||
|
||||
@ -2,6 +2,7 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x80200000
|
||||
@ -11,6 +12,5 @@ CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
|
||||
@ -2,6 +2,7 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -12,7 +13,6 @@ CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SYSRESET_SBI=y
|
||||
|
||||
@ -2,10 +2,11 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
|
||||
CONFIG_SPL=y
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
# CONFIG_OF_BOARD_FIXUP is not set
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x80200000
|
||||
CONFIG_FIT=y
|
||||
@ -14,7 +15,7 @@ CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_SBI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SYSRESET_SBI=y
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
|
||||
@ -2,6 +2,7 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -12,6 +13,5 @@ CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
|
||||
@ -2,6 +2,7 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
@ -15,7 +16,6 @@ CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SYSRESET_SBI=y
|
||||
|
||||
@ -2,7 +2,7 @@ CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
|
||||
CONFIG_SPL=y
|
||||
CONFIG_TARGET_QEMU_VIRT=y
|
||||
CONFIG_ARCH_RV64I=y
|
||||
@ -15,7 +15,7 @@ CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_CMD_SBI=y
|
||||
# CONFIG_CMD_MII is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SYSRESET_SBI=y
|
||||
# CONFIG_BINMAN_FDT is not set
|
||||
|
||||
@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64"
|
||||
CONFIG_DEBUG_UART_BASE=0x9000000
|
||||
CONFIG_DEBUG_UART_CLOCK=0
|
||||
CONFIG_DEBUG_UART=y
|
||||
@ -28,7 +29,6 @@ CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0x4000000
|
||||
CONFIG_SCSI_AHCI=y
|
||||
|
||||
@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="qemu-arm"
|
||||
CONFIG_TARGET_QEMU_ARM_32BIT=y
|
||||
CONFIG_DEBUG_UART_BASE=0x9000000
|
||||
CONFIG_DEBUG_UART_CLOCK=0
|
||||
@ -30,7 +31,6 @@ CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0x4000000
|
||||
CONFIG_SCSI_AHCI=y
|
||||
|
||||
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_RPI_4_32B=y
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x1000000
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
@ -20,7 +21,6 @@ CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_FS_UUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
|
||||
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_RPI_4=y
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x1000000
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
@ -20,7 +21,6 @@ CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_FS_UUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
|
||||
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_RPI_ARM64=y
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x1000000
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
@ -19,7 +20,6 @@ CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_FS_UUID=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_TFTP_TSIZE=y
|
||||
|
||||
@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0xff000000
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="juno-r2"
|
||||
CONFIG_IDENT_STRING=" vexpress_aemv8a"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x90000000
|
||||
@ -32,7 +33,6 @@ CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xBFC0000
|
||||
CONFIG_SATA_SIL=y
|
||||
|
||||
@ -3,7 +3,7 @@ CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_TARGET_XENGUEST_ARM64=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40080000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
|
||||
CONFIG_IDENT_STRING=" xenguest"
|
||||
CONFIG_SYS_LOAD_ADDR=0x40000000
|
||||
CONFIG_BOOTDELAY=10
|
||||
@ -33,7 +33,6 @@ CONFIG_CMD_PVBLOCK=y
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
|
||||
|
||||
@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_SYS_MEMTEST_START=0x00000000
|
||||
CONFIG_SYS_MEMTEST_END=0x00001000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
|
||||
CONFIG_CMD_FRU=y
|
||||
CONFIG_DEFINE_TCM_OCM_MMAP=y
|
||||
CONFIG_COUNTER_FREQUENCY=100000000
|
||||
|
||||
@ -21,6 +21,9 @@ The 'virt' platform provides the following as the basic functionality:
|
||||
|
||||
Additionally, a number of optional peripherals can be added to the PCI bus.
|
||||
|
||||
See :doc:`../../develop/devicetree/dt_qemu` for information on how to see
|
||||
the devicetree actually generated by QEMU.
|
||||
|
||||
Building U-Boot
|
||||
---------------
|
||||
Set the CROSS_COMPILE environment variable as usual, and run:
|
||||
@ -41,14 +44,15 @@ The minimal QEMU command line to get U-Boot up and running is:
|
||||
|
||||
- For ARM::
|
||||
|
||||
qemu-system-arm -machine virt -bios u-boot.bin
|
||||
qemu-system-arm -machine virt -nographic -bios u-boot.bin
|
||||
|
||||
- For AArch64::
|
||||
|
||||
qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
|
||||
qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 -bios u-boot.bin
|
||||
|
||||
Note that for some odd reason qemu-system-aarch64 needs to be explicitly
|
||||
told to use a 64-bit CPU or it will boot in 32-bit mode.
|
||||
told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
|
||||
ensures that output appears on the terminal. Use Ctrl-A X to quit.
|
||||
|
||||
Additional persistent U-boot environment support can be added as follows:
|
||||
|
||||
|
||||
@ -13,6 +13,9 @@ The QEMU virt machine models a generic RISC-V virtual machine with support for
|
||||
the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
|
||||
16550A UART devices in addition to VirtIO and it also uses device-tree to pass
|
||||
configuration information to guest software. It implements RISC-V privileged
|
||||
|
||||
See :doc:`../../develop/devicetree/dt_qemu` for information on how to see
|
||||
the devicetree actually generated by QEMU.
|
||||
architecture spec v1.10.
|
||||
|
||||
Building U-Boot
|
||||
|
||||
48
doc/develop/devicetree/dt_qemu.rst
Normal file
48
doc/develop/devicetree/dt_qemu.rst
Normal file
@ -0,0 +1,48 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Devicetree in QEMU
|
||||
==================
|
||||
|
||||
For QEMU on ARM, RISC-V and one PPC target, the devicetree is created on-the-fly
|
||||
by QEMU. It is intended for use in Linux but can be used by U-Boot also, so long
|
||||
as any nodes/properties needed by U-Boot are merged in.
|
||||
|
||||
When `CONFIG_OF_BOARD` is enabled
|
||||
|
||||
|
||||
Obtaining the QEMU devicetree
|
||||
-----------------------------
|
||||
|
||||
Where QEMU generates its own devicetree to pass to U-Boot tou can use
|
||||
`-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version.
|
||||
|
||||
To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`,
|
||||
e.g.::
|
||||
|
||||
qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
|
||||
|
||||
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
|
||||
|
||||
qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb
|
||||
|
||||
|
||||
Merging in U-Boot nodes/properties
|
||||
----------------------------------
|
||||
|
||||
Various U-Boot features require nodes and properties in the U-Boot devicetree
|
||||
and at present QEMU is unaware of these. To use these you must manually merge
|
||||
in the appropriate pieces.
|
||||
|
||||
One way to do this is with dtc. This command runs dtc on each .dtb file in turn,
|
||||
to produce a text file. It drops the duplicate header on the qemu one. Then it
|
||||
joins them up and runs them through dtc to compile the output::
|
||||
|
||||
qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
|
||||
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb u-boot.dtb |grep -v /dts-v1/) |dtc - -o merged.dtb
|
||||
|
||||
You can then run qemu with the merged devicetree, e.g.::
|
||||
|
||||
qemu-system-arm -machine virt -nographic -bios u-boot.bin -dtb merged.dtb
|
||||
|
||||
Note that there seems to be a bug in some versions of qemu where the output of
|
||||
dumpdtb does not quite match what is provided to U-Boot.
|
||||
@ -11,3 +11,4 @@ build-time and runtime configuration.
|
||||
|
||||
intro
|
||||
control
|
||||
dt_qemu
|
||||
|
||||
@ -739,6 +739,17 @@ int device_get_child_count(const struct udevice *parent)
|
||||
return count;
|
||||
}
|
||||
|
||||
int device_get_decendent_count(const struct udevice *parent)
|
||||
{
|
||||
const struct udevice *dev;
|
||||
int count = 1;
|
||||
|
||||
list_for_each_entry(dev, &parent->child_head, sibling_node)
|
||||
count += device_get_decendent_count(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
int device_find_child_by_seq(const struct udevice *parent, int seq,
|
||||
struct udevice **devp)
|
||||
{
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include <dm/read.h>
|
||||
#include <dm/root.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/util.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
@ -407,6 +408,12 @@ int dm_init_and_scan(bool pre_reloc_only)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dm_get_stats(int *device_countp, int *uclass_countp)
|
||||
{
|
||||
*device_countp = device_get_decendent_count(gd->dm_root);
|
||||
*uclass_countp = uclass_get_count();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ACPIGEN
|
||||
static int root_acpi_get_name(const struct udevice *dev, char *out_name)
|
||||
{
|
||||
|
||||
@ -643,6 +643,19 @@ int uclass_next_device_check(struct udevice **devp)
|
||||
return device_probe(*devp);
|
||||
}
|
||||
|
||||
int uclass_get_count(void)
|
||||
{
|
||||
const struct uclass *uc;
|
||||
int count = 0;
|
||||
|
||||
if (gd->dm_root) {
|
||||
list_for_each_entry(uc, gd->uclass_root, sibling_node)
|
||||
count++;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
|
||||
struct udevice **devp)
|
||||
{
|
||||
|
||||
65
dts/Kconfig
65
dts/Kconfig
@ -16,24 +16,6 @@ config BINMAN
|
||||
bool
|
||||
select DTOC
|
||||
|
||||
config BINMAN_STANDALONE_FDT
|
||||
bool
|
||||
depends on BINMAN
|
||||
default y if OF_BOARD
|
||||
help
|
||||
This option tells U-Boot build system that a standalone device tree
|
||||
source is explicitly required when using binman to package U-Boot.
|
||||
|
||||
This is not necessary in a common scenario where a device tree source
|
||||
that contains the binman node is provided in the arch/<arch>/dts
|
||||
directory for a specific board. Such device tree sources are built for
|
||||
OF_SEPARATE or OF_EMBED. However for a scenario like the board device
|
||||
tree blob is not provided in the U-Boot build tree, but fed to U-Boot
|
||||
in the runtime, e.g.: in the OF_BOARD case that it is passed by
|
||||
a prior stage bootloader. For such scenario, a standalone device tree
|
||||
blob containing binman node to describe how to package U-Boot should
|
||||
be provided explicitly.
|
||||
|
||||
menu "Device Tree Control"
|
||||
depends on SUPPORT_OF_CONTROL
|
||||
|
||||
@ -97,11 +79,9 @@ config OF_LIVE
|
||||
choice
|
||||
prompt "Provider of DTB for DT control"
|
||||
depends on OF_CONTROL
|
||||
default OF_BOARD if SANDBOX
|
||||
|
||||
config OF_SEPARATE
|
||||
bool "Separate DTB for DT control"
|
||||
depends on !SANDBOX
|
||||
help
|
||||
If this option is enabled, the device tree will be built and
|
||||
placed as a separate u-boot.dtb file alongside the U-Boot image.
|
||||
@ -114,14 +94,50 @@ config OF_EMBED
|
||||
and development only and is not recommended for production devices.
|
||||
Boards in the mainline U-Boot tree should not use it.
|
||||
|
||||
endchoice
|
||||
|
||||
config OF_BOARD
|
||||
bool "Provided by the board (e.g a previous loader) at runtime"
|
||||
default y if SANDBOX || OF_HAS_PRIOR_STAGE
|
||||
help
|
||||
If this option is enabled, the device tree will be provided by
|
||||
the board at runtime if the board supports it, instead of being
|
||||
bundled with the image.
|
||||
If this option is enabled, the device tree is provided at runtime by
|
||||
a custom function called board_fdt_blob_setup(). The board must
|
||||
implement this function if it wishes to provide special behaviour.
|
||||
|
||||
endchoice
|
||||
With this option, the device tree build by U-Boot may be overridden or
|
||||
ignored. See OF_HAS_PRIOR_STAGE.
|
||||
|
||||
Note: Boards which use this to handle a device tree passed from an
|
||||
earlier stage should enable OF_HAS_PRIOR_STAGE.
|
||||
|
||||
config OF_HAS_PRIOR_STAGE
|
||||
bool
|
||||
help
|
||||
Indicates that a prior stage of the firmware (before U-Boot proper)
|
||||
makes use of device tree and this board normally boots with that prior
|
||||
stage, that provides a devicetree to U-Boot.
|
||||
|
||||
This means that the device tree built in U-Boot should not be packaged
|
||||
in the firmware image. Instead, the prior stage's device tree should
|
||||
be so packaged. At runtime, the prior stage reads this, does any
|
||||
necessary fix-ups, then passes it to U-Boot. See OF_BOARD.
|
||||
|
||||
This option does not preclude using the U-Boot device tree, e.g. for
|
||||
development purposes, but it is not recommended, and likely will not
|
||||
even work, for production systems.
|
||||
|
||||
Note: This option must be set in Kconfig and cannot be enabled or
|
||||
disabled in the board's defconfig file.
|
||||
|
||||
config OF_OMIT_DTB
|
||||
bool "Omit the device tree output when building"
|
||||
default y if OF_HAS_PRIOR_STAGE && !BINMAN
|
||||
help
|
||||
As a special case, avoid writing a device tree file u-boot.dtb when
|
||||
building. Also don't include that file in u-boot.bin
|
||||
|
||||
This is used for boards which normally provide a devicetree via a
|
||||
runtime mechanism (such as OF_BOARD), to avoid confusion.
|
||||
|
||||
config DEFAULT_DEVICE_TREE
|
||||
string "Default Device Tree for DT control"
|
||||
@ -194,7 +210,6 @@ endchoice
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
hex "Size of memory reserved to uncompress the DTBs"
|
||||
depends on (MULTI_DTB_FIT_GZIP || MULTI_DTB_FIT_LZO)
|
||||
default 0x8000
|
||||
help
|
||||
This is the size of this area where the DTBs are uncompressed.
|
||||
|
||||
@ -244,6 +244,10 @@ struct global_data {
|
||||
* @fdt_size: space reserved for relocated device space
|
||||
*/
|
||||
unsigned long fdt_size;
|
||||
/**
|
||||
* @fdt_src: Source of FDT
|
||||
*/
|
||||
enum fdt_source_t fdt_src;
|
||||
#if CONFIG_IS_ENABLED(OF_LIVE)
|
||||
/**
|
||||
* @of_root: root node of the live tree
|
||||
@ -512,6 +516,14 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
|
||||
#define gd_acpi_ctx() NULL
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
#define gd_multi_dtb_fit() gd->multi_dtb_fit
|
||||
#define gd_set_multi_dtb_fit(_dtb) gd->multi_dtb_fit = _dtb
|
||||
#else
|
||||
#define gd_multi_dtb_fit() NULL
|
||||
#define gd_set_multi_dtb_fit(_dtb)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* enum gd_flags - global data flags
|
||||
*
|
||||
|
||||
@ -593,7 +593,7 @@ int device_get_child(const struct udevice *parent, int index,
|
||||
struct udevice **devp);
|
||||
|
||||
/**
|
||||
* device_get_child_count() - Get the available child count of a device
|
||||
* device_get_child_count() - Get the child count of a device
|
||||
*
|
||||
* Returns the number of children to a device.
|
||||
*
|
||||
@ -601,6 +601,15 @@ int device_get_child(const struct udevice *parent, int index,
|
||||
*/
|
||||
int device_get_child_count(const struct udevice *parent);
|
||||
|
||||
/**
|
||||
* device_get_decendent_count() - Get the total number of decendents of a device
|
||||
*
|
||||
* Returns the total number of decendents, including all children
|
||||
*
|
||||
* @parent: Parent device to check
|
||||
*/
|
||||
int device_get_decendent_count(const struct udevice *parent);
|
||||
|
||||
/**
|
||||
* device_find_child_by_seq() - Find a child device based on a sequence
|
||||
*
|
||||
|
||||
@ -131,4 +131,12 @@ int dm_remove_devices_flags(uint flags);
|
||||
static inline int dm_remove_devices_flags(uint flags) { return 0; }
|
||||
#endif
|
||||
|
||||
/**
|
||||
* dm_get_stats() - Get some stats for driver mode
|
||||
*
|
||||
* @device_countp: Returns total number of devices that are bound
|
||||
* @uclass_countp: Returns total number of uclasses in use
|
||||
*/
|
||||
void dm_get_stats(int *device_countp, int *uclass_countp);
|
||||
|
||||
#endif
|
||||
|
||||
@ -306,6 +306,13 @@ int uclass_pre_remove_device(struct udevice *dev);
|
||||
static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; }
|
||||
#endif
|
||||
|
||||
/**
|
||||
* uclass_get_count() - Get the number of uclasses
|
||||
*
|
||||
* Returns the number of uclasses instantiated in driver model
|
||||
*/
|
||||
int uclass_get_count(void);
|
||||
|
||||
/**
|
||||
* uclass_find() - Find uclass by its id
|
||||
*
|
||||
|
||||
@ -58,3 +58,5 @@
|
||||
#define BCM2835_CLOCK_DSI1E 48
|
||||
#define BCM2835_CLOCK_DSI0P 49
|
||||
#define BCM2835_CLOCK_DSI1P 50
|
||||
|
||||
#define BCM2711_CLOCK_EMMC2 51
|
||||
|
||||
@ -55,6 +55,31 @@ struct bd_info;
|
||||
#define SPL_BUILD 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* enum fdt_source_t - indicates where the devicetree came from
|
||||
*
|
||||
* These are listed in approximate order of desirability after FDTSRC_NONE
|
||||
*
|
||||
* @FDTSRC_SEPARATE: Appended to U-Boot. This is the normal approach if U-Boot
|
||||
* is the only firmware being booted
|
||||
* @FDTSRC_FIT: Found in a multi-dtb FIT. This should be used when U-Boot must
|
||||
* select a devicetree from many options
|
||||
* @FDTSRC_BOARD: Located by custom board code. This should only be used when
|
||||
* the prior stage does not support FDTSRC_PASSAGE
|
||||
* @FDTSRC_EMBED: Embedded into U-Boot executable. This should onyl be used when
|
||||
* U-Boot is packaged as an ELF file, e.g. for debugging purposes
|
||||
* @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should
|
||||
* be used for debugging/development only
|
||||
* @FDTSRC_NONE: No devicetree at all
|
||||
*/
|
||||
enum fdt_source_t {
|
||||
FDTSRC_SEPARATE,
|
||||
FDTSRC_FIT,
|
||||
FDTSRC_BOARD,
|
||||
FDTSRC_EMBED,
|
||||
FDTSRC_ENV,
|
||||
};
|
||||
|
||||
/*
|
||||
* Information about a resource. start is the first address of the resource
|
||||
* and end is the last address (inclusive). The length of the resource will
|
||||
@ -111,6 +136,20 @@ struct fdt_pci_addr {
|
||||
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
|
||||
extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
|
||||
|
||||
/* Get a pointer to the embedded devicetree, if there is one, else NULL */
|
||||
static inline u8 *dtb_dt_embedded(void)
|
||||
{
|
||||
#ifdef CONFIG_OF_EMBED
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
return __dtb_dt_spl_begin;
|
||||
# else
|
||||
return __dtb_dt_begin;
|
||||
# endif
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Compute the size of a resource.
|
||||
*
|
||||
@ -1156,10 +1195,13 @@ int fdtdec_resetup(int *rescan);
|
||||
|
||||
/**
|
||||
* Board-specific FDT initialization. Returns the address to a device tree blob.
|
||||
* Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
|
||||
* and the board implements it.
|
||||
*
|
||||
* Called when CONFIG_OF_BOARD is defined.
|
||||
*
|
||||
* The existing devicetree is available at gd->fdt_blob
|
||||
*
|
||||
* @err internal error code if we fail to setup a DTB
|
||||
* @returns new devicetree blob pointer
|
||||
*/
|
||||
void *board_fdt_blob_setup(int *err);
|
||||
|
||||
@ -1198,4 +1240,11 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
|
||||
phys_addr_t *basep, phys_size_t *sizep,
|
||||
struct bd_info *bd);
|
||||
|
||||
/**
|
||||
* fdtdec_get_srcname() - Get the name of where the devicetree comes from
|
||||
*
|
||||
* @return source name
|
||||
*/
|
||||
const char *fdtdec_get_srcname(void);
|
||||
|
||||
#endif
|
||||
|
||||
141
lib/fdtdec.c
141
lib/fdtdec.c
@ -76,6 +76,19 @@ static const char * const compat_names[COMPAT_COUNT] = {
|
||||
COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
|
||||
};
|
||||
|
||||
static const char *const fdt_src_name[] = {
|
||||
[FDTSRC_SEPARATE] = "separate",
|
||||
[FDTSRC_FIT] = "fit",
|
||||
[FDTSRC_BOARD] = "board",
|
||||
[FDTSRC_EMBED] = "embed",
|
||||
[FDTSRC_ENV] = "env",
|
||||
};
|
||||
|
||||
const char *fdtdec_get_srcname(void)
|
||||
{
|
||||
return fdt_src_name[gd->fdt_src];
|
||||
}
|
||||
|
||||
const char *fdtdec_get_compatible(enum fdt_compat_id id)
|
||||
{
|
||||
/* We allow reading of the 'unknown' ID for testing purposes */
|
||||
@ -1146,11 +1159,10 @@ int fdtdec_setup_mem_size_base_lowest(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
|
||||
CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
|
||||
static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
|
||||
CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
|
||||
size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
|
||||
bool gzip = 0, lzo = 0;
|
||||
ulong sz_in = sz_src;
|
||||
@ -1175,11 +1187,11 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
|
||||
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
|
||||
dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
|
||||
# else
|
||||
# else
|
||||
return -ENOTSUPP;
|
||||
# endif
|
||||
# endif
|
||||
}
|
||||
|
||||
if (CONFIG_IS_ENABLED(GZIP) && gzip)
|
||||
@ -1197,27 +1209,22 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
return -EBADMSG;
|
||||
}
|
||||
*dstp = dst;
|
||||
return 0;
|
||||
}
|
||||
# else
|
||||
static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
{
|
||||
#else
|
||||
*dstp = (void *)src;
|
||||
*dstp = (void *)src;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
|
||||
/*
|
||||
* For CONFIG_OF_SEPARATE, the board may optionally implement this to
|
||||
* provide and/or fixup the fdt.
|
||||
/**
|
||||
* fdt_find_separate() - Find a devicetree at the end of the image
|
||||
*
|
||||
* @return pointer to FDT blob
|
||||
*/
|
||||
__weak void *board_fdt_blob_setup(int *err)
|
||||
static void *fdt_find_separate(void)
|
||||
{
|
||||
void *fdt_blob = NULL;
|
||||
|
||||
*err = 0;
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* FDT is at end of BSS unless it is in a different memory region */
|
||||
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
|
||||
@ -1231,7 +1238,6 @@ __weak void *board_fdt_blob_setup(int *err)
|
||||
|
||||
return fdt_blob;
|
||||
}
|
||||
#endif
|
||||
|
||||
int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
|
||||
{
|
||||
@ -1589,60 +1595,81 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TODO(sjg@chromium.org): This function should not be weak */
|
||||
__weak int fdtdec_board_setup(const void *fdt_blob)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fdtdec_setup(void)
|
||||
/**
|
||||
* setup_multi_dtb_fit() - locate the correct dtb from a FIT
|
||||
*
|
||||
* This supports the CONFIG_MULTI_DTB_FIT feature, looking for the dtb in a
|
||||
* supplied FIT
|
||||
*
|
||||
* It accepts the current value of gd->fdt_blob, which points to the FIT, then
|
||||
* updates that gd->fdt_blob, to point to the chosen dtb so that U-Boot uses the
|
||||
* correct one
|
||||
*/
|
||||
static void setup_multi_dtb_fit(void)
|
||||
{
|
||||
int ret;
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
void *fdt_blob;
|
||||
# endif
|
||||
# ifdef CONFIG_OF_EMBED
|
||||
/* Get a pointer to the FDT */
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
gd->fdt_blob = __dtb_dt_spl_begin;
|
||||
# else
|
||||
gd->fdt_blob = __dtb_dt_begin;
|
||||
# endif
|
||||
# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
|
||||
/* Allow the board to override the fdt address. */
|
||||
gd->fdt_blob = board_fdt_blob_setup(&ret);
|
||||
if (ret)
|
||||
return ret;
|
||||
# endif
|
||||
# ifndef CONFIG_SPL_BUILD
|
||||
/* Allow the early environment to override the fdt address */
|
||||
gd->fdt_blob = map_sysmem
|
||||
(env_get_ulong("fdtcontroladdr", 16,
|
||||
(unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
|
||||
# endif
|
||||
void *blob;
|
||||
|
||||
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
/*
|
||||
* Try and uncompress the blob.
|
||||
* Unfortunately there is no way to know how big the input blob really
|
||||
* is. So let us set the maximum input size arbitrarily high. 16MB
|
||||
* ought to be more than enough for packed DTBs.
|
||||
*/
|
||||
if (uncompress_blob(gd->fdt_blob, 0x1000000, &fdt_blob) == 0)
|
||||
gd->fdt_blob = fdt_blob;
|
||||
if (uncompress_blob(gd->fdt_blob, 0x1000000, &blob) == 0)
|
||||
gd->fdt_blob = blob;
|
||||
|
||||
/*
|
||||
* Check if blob is a FIT images containings DTBs.
|
||||
* If so, pick the most relevant
|
||||
*/
|
||||
fdt_blob = locate_dtb_in_fit(gd->fdt_blob);
|
||||
if (fdt_blob) {
|
||||
gd->multi_dtb_fit = gd->fdt_blob;
|
||||
gd->fdt_blob = fdt_blob;
|
||||
blob = locate_dtb_in_fit(gd->fdt_blob);
|
||||
if (blob) {
|
||||
gd_set_multi_dtb_fit(gd->fdt_blob);
|
||||
gd->fdt_blob = blob;
|
||||
gd->fdt_src = FDTSRC_FIT;
|
||||
}
|
||||
}
|
||||
|
||||
int fdtdec_setup(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* The devicetree is typically appended to U-Boot */
|
||||
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
|
||||
gd->fdt_blob = fdt_find_separate();
|
||||
gd->fdt_src = FDTSRC_SEPARATE;
|
||||
} else { /* embed dtb in ELF file for testing / development */
|
||||
gd->fdt_blob = dtb_dt_embedded();
|
||||
gd->fdt_src = FDTSRC_EMBED;
|
||||
}
|
||||
|
||||
# endif
|
||||
#endif
|
||||
/* Allow the board to override the fdt address. */
|
||||
if (IS_ENABLED(CONFIG_OF_BOARD)) {
|
||||
gd->fdt_blob = board_fdt_blob_setup(&ret);
|
||||
if (ret)
|
||||
return ret;
|
||||
gd->fdt_src = FDTSRC_BOARD;
|
||||
}
|
||||
|
||||
/* Allow the early environment to override the fdt address */
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
ulong addr;
|
||||
|
||||
addr = env_get_hex("fdtcontroladdr", 0);
|
||||
if (addr) {
|
||||
gd->fdt_blob = map_sysmem(addr, 0);
|
||||
gd->fdt_src = FDTSRC_ENV;
|
||||
}
|
||||
}
|
||||
|
||||
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
|
||||
setup_multi_dtb_fit();
|
||||
|
||||
ret = fdtdec_prepare_fdt();
|
||||
if (!ret)
|
||||
@ -1650,7 +1677,6 @@ int fdtdec_setup(void)
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
int fdtdec_resetup(int *rescan)
|
||||
{
|
||||
void *fdt_blob;
|
||||
@ -1661,8 +1687,8 @@ int fdtdec_resetup(int *rescan)
|
||||
* FIT image stillpresent there. Save the time and space
|
||||
* required to uncompress it again.
|
||||
*/
|
||||
if (gd->multi_dtb_fit) {
|
||||
fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit);
|
||||
if (gd_multi_dtb_fit()) {
|
||||
fdt_blob = locate_dtb_in_fit(gd_multi_dtb_fit());
|
||||
|
||||
if (fdt_blob == gd->fdt_blob) {
|
||||
/*
|
||||
@ -1686,7 +1712,6 @@ int fdtdec_resetup(int *rescan)
|
||||
*rescan = 0;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
|
||||
phys_addr_t *basep, phys_size_t *sizep,
|
||||
|
||||
@ -175,7 +175,9 @@ u_boot_dtsi_options_raw = $(warning Automatic .dtsi inclusion: options: \
|
||||
|
||||
# Uncomment for debugging
|
||||
# This shows all the files that were considered and the one that we chose.
|
||||
# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
|
||||
ifdef DEVICE_TREE_DEBUG
|
||||
u_boot_dtsi_options_debug = $(warning $(u_boot_dtsi_options_raw))
|
||||
endif
|
||||
|
||||
# We use the first match
|
||||
u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
|
||||
|
||||
42
scripts/check-of.sh
Executable file
42
scripts/check-of.sh
Executable file
@ -0,0 +1,42 @@
|
||||
#!/bin/sh
|
||||
# Copyright 2021 Google LLC
|
||||
# Written by Simon Glass <sjg@chromium.org>
|
||||
#
|
||||
# Check that the .config file provided does not try to disable OF_BOARD for
|
||||
# boards that use CONFIG_OF_HAS_PRIOR_STAGE
|
||||
#
|
||||
# Usage
|
||||
# check-of.sh <path to .config> <path to allowlist file>
|
||||
#
|
||||
# For example:
|
||||
# scripts/check-of.sh b/chromebook_link/u-boot.cfg kconfig_allowlist.txt
|
||||
#
|
||||
# Exit code is 0 if OK, 3 if the .config is wrong, as above
|
||||
|
||||
set -e
|
||||
set -u
|
||||
|
||||
PROG_NAME="${0##*/}"
|
||||
|
||||
usage() {
|
||||
echo "$PROG_NAME <path to .config> <path to allowlist file>"
|
||||
exit 1
|
||||
}
|
||||
|
||||
[ $# -ge 2 ] || usage
|
||||
|
||||
path="$1"
|
||||
allowlist="$2"
|
||||
|
||||
sys_config="$(sed -n 's/CONFIG_SYS_CONFIG_NAME="\(.*\)"$/\1/p' "${path}")"
|
||||
|
||||
if grep -q OF_HAS_PRIOR_STAGE=y "${path}"; then
|
||||
if ! grep -lq CONFIG_OF_BOARD=y "${path}"; then
|
||||
echo >&2 "This board uses a prior stage to provide the device tree."
|
||||
echo >&2 "Please enable CONFIG_OF_BOARD to ensure that it works correctly."
|
||||
if grep -q "${sys_config}" "${allowlist}"; then
|
||||
exit 0
|
||||
fi
|
||||
exit 3
|
||||
fi
|
||||
fi
|
||||
1
scripts/of_allowlist.txt
Normal file
1
scripts/of_allowlist.txt
Normal file
@ -0,0 +1 @@
|
||||
# List of boards which are permitted to use OF_HAS_PRIOR_STAGE without OF_BOARD
|
||||
@ -307,11 +307,15 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
|
||||
{
|
||||
int op_count[DM_TEST_OP_COUNT];
|
||||
struct udevice *dev, *test_dev;
|
||||
int start_dev_count, start_uc_count;
|
||||
int dev_count, uc_count;
|
||||
int pingret;
|
||||
int ret;
|
||||
|
||||
memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
|
||||
|
||||
dm_get_stats(&start_dev_count, &start_uc_count);
|
||||
|
||||
ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual,
|
||||
&dev));
|
||||
ut_assert(dev);
|
||||
@ -319,6 +323,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
|
||||
== op_count[DM_TEST_OP_BIND] + 1);
|
||||
ut_assert(!dev_get_priv(dev));
|
||||
|
||||
/* We should have one more device */
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_asserteq(start_dev_count + 1, dev_count);
|
||||
ut_asserteq(start_uc_count, uc_count);
|
||||
|
||||
/* Probe the device - it should fail allocating private data */
|
||||
uts->force_fail_alloc = 1;
|
||||
ret = device_probe(dev);
|
||||
@ -353,6 +362,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
|
||||
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
|
||||
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
|
||||
|
||||
/* We should have one less device */
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_asserteq(start_dev_count, dev_count);
|
||||
ut_asserteq(start_uc_count, uc_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DM_TEST(dm_test_lifecycle, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
|
||||
@ -526,17 +540,31 @@ DM_TEST(dm_test_leak, 0);
|
||||
/* Test uclass init/destroy methods */
|
||||
static int dm_test_uclass(struct unit_test_state *uts)
|
||||
{
|
||||
int dev_count, uc_count;
|
||||
struct uclass *uc;
|
||||
|
||||
/* We should have just the root device and uclass */
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_asserteq(1, dev_count);
|
||||
ut_asserteq(1, uc_count);
|
||||
|
||||
ut_assertok(uclass_get(UCLASS_TEST, &uc));
|
||||
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
|
||||
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
|
||||
ut_assert(uclass_get_priv(uc));
|
||||
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_asserteq(1, dev_count);
|
||||
ut_asserteq(2, uc_count);
|
||||
|
||||
ut_assertok(uclass_destroy(uc));
|
||||
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
|
||||
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
|
||||
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_asserteq(1, dev_count);
|
||||
ut_asserteq(1, uc_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DM_TEST(dm_test_uclass, 0);
|
||||
@ -1217,3 +1245,16 @@ static int dm_test_dma_offset(struct unit_test_state *uts)
|
||||
}
|
||||
DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
|
||||
#endif
|
||||
|
||||
/* Test dm_get_stats() */
|
||||
static int dm_test_get_stats(struct unit_test_state *uts)
|
||||
{
|
||||
int dev_count, uc_count;
|
||||
|
||||
dm_get_stats(&dev_count, &uc_count);
|
||||
ut_assert(dev_count > 50);
|
||||
ut_assert(uc_count > 30);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DM_TEST(dm_test_get_stats, UT_TESTF_SCAN_FDT);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user