i2c: Add support for Renesas rcar
This supports i2c controller for Renesas rcar. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This commit is contained in:
Nobuhiro Iwamatsu
Heiko Schocher
parent
e66587495d
commit
1086bfa9f4
14
README
14
README
@ -2014,6 +2014,20 @@ CBFS (Coreboot Filesystem) support
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If thoses defines are not set, default value is 100000
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for speed, and 0 for slave.
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- drivers/i2c/rcar_i2c.c:
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- activate this driver with CONFIG_SYS_I2C_RCAR
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- This driver adds 4 i2c buses
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- CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
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- CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
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- CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
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- CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
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- CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
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- CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
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- CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
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- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
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- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -29,6 +29,7 @@ COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
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288
drivers/i2c/rcar_i2c.c
Normal file
288
drivers/i2c/rcar_i2c.c
Normal file
@ -0,0 +1,288 @@
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/*
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* drivers/i2c/rcar_i2c.c
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rcar_i2c {
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u32 icscr;
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u32 icmcr;
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u32 icssr;
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u32 icmsr;
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u32 icsier;
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u32 icmier;
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u32 icccr;
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u32 icsar;
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u32 icmar;
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u32 icrxdtxd;
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u32 icccr2;
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u32 icmpr;
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u32 ichpr;
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u32 iclpr;
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};
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#define MCR_MDBS 0x80 /* non-fifo mode switch */
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#define MCR_FSCL 0x40 /* override SCL pin */
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#define MCR_FSDA 0x20 /* override SDA pin */
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#define MCR_OBPC 0x10 /* override pins */
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#define MCR_MIE 0x08 /* master if enable */
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#define MCR_TSBE 0x04
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#define MCR_FSB 0x02 /* force stop bit */
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#define MCR_ESG 0x01 /* en startbit gen. */
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#define MSR_MASK 0x7f
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#define MSR_MNR 0x40 /* nack received */
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#define MSR_MAL 0x20 /* arbitration lost */
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#define MSR_MST 0x10 /* sent a stop */
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#define MSR_MDE 0x08
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#define MSR_MDT 0x04
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#define MSR_MDR 0x02
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#define MSR_MAT 0x01 /* slave addr xfer done */
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static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
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(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
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(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
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(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
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(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
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};
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static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
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{
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/* set slave address */
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writel(chip << 1, &dev->icmar);
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/* set register address */
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writel(addr, &dev->icrxdtxd);
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/* clear status */
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writel(0, &dev->icmsr);
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/* start master send */
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writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
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while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
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!= (MSR_MAT | MSR_MDE))
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udelay(10);
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/* clear ESG */
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writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
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/* start SCLclk */
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writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
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while (!(readl(&dev->icmsr) & MSR_MDE))
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udelay(10);
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}
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static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
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{
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while (!(readl(&dev->icmsr) & MSR_MST))
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udelay(10);
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writel(0, &dev->icmcr);
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}
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static int
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rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
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{
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rcar_i2c_raw_rw_common(dev, chip, addr);
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/* set send date */
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writel(*val, &dev->icrxdtxd);
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/* start SCLclk */
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writel(~MSR_MDE, &dev->icmsr);
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while (!(readl(&dev->icmsr) & MSR_MDE))
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udelay(10);
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/* set stop condition */
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writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
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/* start SCLclk */
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writel(~MSR_MDE, &dev->icmsr);
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rcar_i2c_raw_rw_finish(dev);
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return 0;
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}
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static u8
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rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
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{
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u8 ret;
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rcar_i2c_raw_rw_common(dev, chip, addr);
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/* set slave address, receive */
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writel((chip << 1) | 1, &dev->icmar);
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/* start master receive */
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writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
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while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
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!= (MSR_MAT | MSR_MDE))
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udelay(10);
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/* clear ESG */
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writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
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/* prepare stop condition */
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writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
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/* start SCLclk */
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writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
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while (!(readl(&dev->icmsr) & MSR_MDR))
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udelay(10);
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/* get receive data */
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ret = (u8)readl(&dev->icrxdtxd);
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/* start SCLclk */
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writel(~MSR_MDR, &dev->icmsr);
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rcar_i2c_raw_rw_finish(dev);
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return ret;
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}
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/*
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* SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
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* iicck : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time: 35 ns
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* tr : I2C SCL rising time: 200 ns
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* intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
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* F[n] : n rounded up to an integer
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*/
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static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
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{
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u32 iicck, f, scl, scgd;
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u32 intd = 5;
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int bit = 0, cdf_width = 3;
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for (bit = 0; bit < (1 << cdf_width); bit++) {
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iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
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if (iicck < 20000000)
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break;
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}
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if (bit > (1 << cdf_width)) {
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puts("rcar-i2c: Can not get CDF\n");
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return 0;
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}
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if (i2c_no == 0)
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intd = 50;
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f = (35 + 200 + intd) * (iicck / 1000000000);
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for (scgd = 0; scgd < 0x40; scgd++) {
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scl = iicck / (20 + (scgd * 8) + f);
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if (scl <= bus_speed)
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break;
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}
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if (scgd > 0x40) {
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puts("rcar-i2c: Can not get SDGB\n");
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return 0;
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}
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debug("%s: scl: %d\n", __func__, scl);
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debug("%s: bit %x\n", __func__, bit);
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debug("%s: scgd %x\n", __func__, scgd);
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debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
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return scgd << (cdf_width) | bit;
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}
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static void
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rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
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u32 icccr = 0;
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/* No i2c support prior to relocation */
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if (!(gd->flags & GD_FLG_RELOC))
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return;
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/*
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* reset slave mode.
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* slave mode is not used on this driver
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*/
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writel(0, &dev->icsier);
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writel(0, &dev->icsar);
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writel(0, &dev->icscr);
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writel(0, &dev->icssr);
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/* reset master mode */
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writel(0, &dev->icmier);
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writel(0, &dev->icmcr);
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writel(0, &dev->icmsr);
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writel(0, &dev->icmar);
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icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
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if (icccr == 0)
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puts("I2C: Init failed\n");
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else
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writel(icccr, &dev->icccr);
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}
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static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, u8 *data, int len)
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{
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struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
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int i;
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for (i = 0; i < len; i++)
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data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
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return 0;
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}
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static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
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int alen, u8 *data, int len)
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{
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struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
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return rcar_i2c_raw_write(dev, chip, addr, data, len);
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}
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static int
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rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
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{
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return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
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}
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static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
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u32 icccr;
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int ret = 0;
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rcar_i2c_raw_rw_finish(dev);
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icccr = rcar_clock_gen(adap->hwadapnr, speed);
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if (icccr == 0) {
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puts("I2C: Init failed\n");
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ret = -1;
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} else {
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writel(icccr, &dev->icccr);
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}
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return ret;
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}
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/*
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* Register RCAR i2c adapters
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*/
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U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
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rcar_i2c_write, rcar_i2c_set_bus_speed,
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CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
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U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
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rcar_i2c_write, rcar_i2c_set_bus_speed,
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CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
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U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
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rcar_i2c_write, rcar_i2c_set_bus_speed,
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CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
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U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
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rcar_i2c_write, rcar_i2c_set_bus_speed,
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CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)
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