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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini 2015-09-02 10:39:28 -04:00
commit 0ffadab1b9
129 changed files with 4145 additions and 604 deletions
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140
arch/arm/Kconfig
View File

@ -62,6 +62,12 @@ config SEMIHOSTING
the hosted environment to call out to the emulator to
retrieve files from the host machine.
config SYS_L2CACHE_OFF
bool "L2cache off"
help
If SoC does not support L2CACHE or one do not want to enable
L2CACHE, choose this option.
choice
prompt "Target select"
default ARCH_VERSATILE
@ -511,112 +517,6 @@ config TARGET_VISION2
bool "Support vision2"
select CPU_V7
config TARGET_UDOO
bool "Support udoo"
select CPU_V7
config TARGET_WANDBOARD
bool "Support wandboard"
select CPU_V7
select SUPPORT_SPL
config TARGET_WARP
bool "Support WaRP"
select CPU_V7
config TARGET_TITANIUM
bool "Support titanium"
select CPU_V7
config TARGET_NITROGEN6X
bool "Support nitrogen6x"
select CPU_V7
config TARGET_CGTQMX6EVAL
bool "Support cgtqmx6eval"
select CPU_V7
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
select CPU_V7
config TARGET_ARISTAINETOS
bool "Support aristainetos"
select CPU_V7
config TARGET_ARISTAINETOS2
bool "Support aristainetos2"
select CPU_V7
config TARGET_MX6QARM2
bool "Support mx6qarm2"
select CPU_V7
config TARGET_MX6QSABREAUTO
bool "Support mx6qsabreauto"
select CPU_V7
select DM
select DM_THERMAL
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6CUBOXI
bool "Support Solid-run mx6 boards"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6SLEVK
bool "Support mx6slevk"
select CPU_V7
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6UL_14X14_EVK
bool "Support mx6ul_14x14_evk"
select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_GW_VENTANA
bool "Support gw_ventana"
select CPU_V7
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Support Kosagi Novena"
select CPU_V7
select SUPPORT_SPL
config TARGET_TBS2910
bool "Support tbs2910"
select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "Support platinum-picon"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "Support platinum-titanium"
select CPU_V7
select SUPPORT_SPL
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
@ -666,6 +566,10 @@ config TARGET_SNOWBALL
bool "Support snowball"
select CPU_V7
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
select CPU_V7
@ -883,7 +787,6 @@ source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/imx-common/Kconfig"
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
@ -894,26 +797,17 @@ source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
@ -931,14 +825,7 @@ source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
@ -948,7 +835,6 @@ source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
@ -968,7 +854,6 @@ source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
@ -980,7 +865,6 @@ source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
@ -990,12 +874,10 @@ source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"

2
arch/arm/cpu/arm1136/mx31/generic.c
View File

@ -175,7 +175,7 @@ u32 get_cpu_rev(void)
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
return mx31_cpu_type[i].v;
return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
return srev | 0x8000;
}

6
arch/arm/cpu/arm926ejs/mx27/generic.c
View File

@ -12,6 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/imx-common/sys_proto.h>
#ifdef CONFIG_MXC_MMC
#include <asm/arch/mxcmmc.h>
#endif
@ -159,6 +160,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
}
u32 get_cpu_rev(void)
{
return MXC_CPU_MX27 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{

10
arch/arm/cpu/arm926ejs/mxs/Makefile
View File

@ -74,12 +74,10 @@ u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
%.sig: %.csf
$(call if_changed,mkcst_mxs)
quiet_cmd_mkimage_mxs = MKIMAGE $@
cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage
u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage_mxs)
$(call if_changed,mkimage)
MKIMAGEFLAGS_u-boot-signed.sb = -n $< -T mxsimage
u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
$(call if_changed,mkimage_mxs)
$(call if_changed,mkimage)

52
arch/arm/cpu/arm926ejs/mxs/mxs.c
View File

@ -132,23 +132,7 @@ int arch_cpu_init(void)
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
static const char *get_cpu_type(void)
{
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX23:
return "23";
case HW_DIGCTL_CHIPID_MX28:
return "28";
default:
return "??";
}
}
static const char *get_cpu_rev(void)
u32 get_cpu_rev(void)
{
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
@ -158,25 +142,34 @@ static const char *get_cpu_rev(void)
case HW_DIGCTL_CHIPID_MX23:
switch (rev) {
case 0x0:
return "1.0";
case 0x1:
return "1.1";
case 0x2:
return "1.2";
case 0x3:
return "1.3";
case 0x4:
return "1.4";
return (MXC_CPU_MX23 << 12) | (rev + 0x10);
default:
return "??";
return 0;
}
case HW_DIGCTL_CHIPID_MX28:
switch (rev) {
case 0x1:
return "1.2";
return (MXC_CPU_MX28 << 12) | 0x12;
default:
return "??";
return 0;
}
default:
return 0;
}
}
#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_MX23:
return "23"; /* Quad-Plus version of the mx6 */
case MXC_CPU_MX28:
return "28"; /* Dual-Plus version of the mx6 */
default:
return "??";
}
@ -184,12 +177,15 @@ static const char *get_cpu_rev(void)
int print_cpuinfo(void)
{
u32 cpurev;
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
get_cpu_type(),
get_cpu_rev(),
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0;

138
arch/arm/cpu/armv7/mx6/Kconfig
View File

@ -33,25 +33,159 @@ choice
prompt "MX6 board select"
optional
config TARGET_ARISTAINETOS
bool "aristainetos"
select CPU_V7
config TARGET_ARISTAINETOS2
bool "aristainetos2"
select CPU_V7
config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
select CPU_V7
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
select CPU_V7
config TARGET_CM_FX6
bool "Support CM-FX6"
bool "CM-FX6"
select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
select CPU_V7
config TARGET_GW_VENTANA
bool "gw_ventana"
select CPU_V7
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
select CPU_V7
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select CPU_V7
select DM
select DM_THERMAL
config TARGET_MX6SABRESD
bool "mx6sabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SLEVK
bool "mx6slevk"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select MX6UL
select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_NITROGEN6X
bool "nitrogen6x"
select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "platinum-picon"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
select CPU_V7
select SUPPORT_SPL
config TARGET_SECOMX6
bool "Support secomx6 boards"
bool "secomx6 boards"
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
select CPU_V7
config TARGET_TITANIUM
bool "titanium"
select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config TARGET_UDOO
bool "udoo"
select CPU_V7
select SUPPORT_SPL
config TARGET_WANDBOARD
bool "wandboard"
select CPU_V7
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
select CPU_V7
endchoice
config SYS_SOC
default "mx6"
source "board/aristainetos/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/udoo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
endif

23
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
#endif
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= freq;
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
if (!(is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL)))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
} else {
return -EINVAL;
}
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
}
/* Enable FEC clock */
reg |= BM_ANADIG_PLL_ENET_ENABLE;
if (fec_id == 0)
reg |= BM_ANADIG_PLL_ENET_ENABLE;
else
reg |= BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);

379
arch/arm/cpu/armv7/mx6/ddr.c
View File

@ -7,6 +7,7 @@
#include <common.h>
#include <linux/types.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
@ -115,6 +116,61 @@ void mx6ul_dram_iocfg(unsigned width,
}
#endif
#if defined(CONFIG_MX6SL)
void mx6sl_dram_iocfg(unsigned width,
const struct mx6sl_iomux_ddr_regs *ddr,
const struct mx6sl_iomux_grp_regs *grp)
{
struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
/* DDR IO TYPE */
mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
/* CLOCK */
mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
/* ADDRESS */
mx6_ddr_iomux->dram_cas = ddr->dram_cas;
mx6_ddr_iomux->dram_ras = ddr->dram_ras;
mx6_grp_iomux->grp_addds = grp->grp_addds;
/* Control */
mx6_ddr_iomux->dram_reset = ddr->dram_reset;
mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
/* Data Strobes */
mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
if (width >= 32) {
mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
}
/* Data */
mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
if (width >= 32) {
mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
}
mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
if (width >= 32) {
mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
}
}
#endif
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
@ -275,24 +331,314 @@ void mx6sdl_dram_iocfg(unsigned width,
* Configure mx6 mmdc registers based on:
* - board-specific memory configuration
* - board-specific calibration data
* - ddr3 chip details
* - ddr3/lpddr2 chip details
*
* The various calculations here are derived from the Freescale
* i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
* configuration registers based on memory system and memory chip parameters.
* 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
* MMDC configuration registers based on memory system and memory chip
* parameters.
*
* 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
* configuration registers based on memory system and memory chip
* parameters.
*
* The defaults here are those which were specified in the spreadsheet.
* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
* section titled MMDC initialization
* and/or IMX6SLRM section titled MMDC initialization.
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
!is_cpu_type(MXC_CPU_MX6SL)) \
mmdc1->entry = value; \
} while (0)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
*/
static int lpddr2_wl(uint32_t mem_speed)
{
switch (mem_speed) {
case 1066:
case 933:
return 4;
case 800:
return 3;
case 677:
case 533:
return 2;
case 400:
case 333:
return 1;
default:
puts("invalid memory speed\n");
hang();
}
return 0;
}
/*
* According JESD209-2B-LPDDR2: Table 103
* RL: read latency
*/
static int lpddr2_rl(uint32_t mem_speed)
{
switch (mem_speed) {
case 1066:
return 8;
case 933:
return 7;
case 800:
return 6;
case 677:
return 5;
case 533:
return 4;
case 400:
case 333:
return 3;
default:
puts("invalid memory speed\n");
hang();
}
return 0;
}
void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_lpddr2_cfg *lpddr2_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
u32 val;
u8 tcke, tcksrx, tcksre, trrd;
u8 twl, txp, tfaw, tcl;
u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
u16 cs0_end;
u8 coladdr;
int clkper; /* clock period in picoseconds */
int clock; /* clock freq in mHz */
int cs;
/* only support 16/32 bits */
if (sysinfo->dsize > 1)
hang();
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
clkper = (1000 * 1000) / clock; /* pico seconds */
twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
/* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
switch (lpddr2_cfg->density) {
case 1:
case 2:
case 4:
trfc = DIV_ROUND_UP(130000, clkper) - 1;
txsr = DIV_ROUND_UP(140000, clkper) - 1;
break;
case 8:
trfc = DIV_ROUND_UP(210000, clkper) - 1;
txsr = DIV_ROUND_UP(220000, clkper) - 1;
break;
default:
/*
* 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
*/
hang();
break;
}
/*
* txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
* set them to 0. */
txp = DIV_ROUND_UP(7500, clkper) - 1;
tcke = 3;
if (lpddr2_cfg->mem_speed == 333)
tfaw = DIV_ROUND_UP(60000, clkper) - 1;
else
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(10000, clkper) - 1;
/* tckesr for LPDDR2 */
tcksre = DIV_ROUND_UP(15000, clkper);
tcksrx = tcksre;
twr = DIV_ROUND_UP(15000, clkper) - 1;
/*
* tMRR: 2, tMRW: 5
* tMRD should be set to max(tMRR, tMRW)
*/
tmrd = 5;
tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
/* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
clkper / 10) - 1;
trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
/* To LPDDR2, CL in MDCFG0 refers to RL */
tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
twtr = DIV_ROUND_UP(7500, clkper) - 1;
trtp = DIV_ROUND_UP(7500, clkper) - 1;
cs0_end = 4 * sysinfo->cs_density - 1;
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, lpddr2_cfg->density);
debug("clock: %dMHz (%d ps)\n", clock, clkper);
debug("memspd:%d\n", lpddr2_cfg->mem_speed);
debug("trcd_lp=%d\n", trcd_lp);
debug("trppb_lp=%d\n", trppb_lp);
debug("trpab_lp=%d\n", trpab_lp);
debug("trc_lp=%d\n", trc_lp);
debug("tcke=%d\n", tcke);
debug("tcksrx=%d\n", tcksrx);
debug("tcksre=%d\n", tcksre);
debug("trfc=%d\n", trfc);
debug("txsr=%d\n", txsr);
debug("txp=%d\n", txp);
debug("tfaw=%d\n", tfaw);
debug("tcl=%d\n", tcl);
debug("tras=%d\n", tras);
debug("twr=%d\n", twr);
debug("tmrd=%d\n", tmrd);
debug("twl=%d\n", twl);
debug("trtp=%d\n", trtp);
debug("twtr=%d\n", twtr);
debug("trrd=%d\n", trrd);
debug("cs0_end=%d\n", cs0_end);
debug("ncs=%d\n", sysinfo->ncs);
/*
* board-specific configuration:
* These values are determined empirically and vary per board layout
*/
mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
/* Read data DQ Byte0-3 delay */
mmdc0->mprddqby0dl = 0x33333333;
mmdc0->mprddqby1dl = 0x33333333;
if (sysinfo->dsize > 0) {
mmdc0->mprddqby2dl = 0x33333333;
mmdc0->mprddqby3dl = 0x33333333;
}
/* Write data DQ Byte0-3 delay */
mmdc0->mpwrdqby0dl = 0xf3333333;
mmdc0->mpwrdqby1dl = 0xf3333333;
if (sysinfo->dsize > 0) {
mmdc0->mpwrdqby2dl = 0xf3333333;
mmdc0->mpwrdqby3dl = 0xf3333333;
}
/*
* In LPDDR2 mode this register should be cleared,
* so no termination will be activated.
*/
mmdc0->mpodtctrl = 0;
/* complete calibration */
val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = val;
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
/* Step 2: Timing configuration */
mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
(tfaw << 4) | tcl;
mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
(trppb_lp << 4) | trpab_lp;
mmdc0->mdotc = 0;
mmdc0->mdasp = cs0_end; /* CS addressing */
/* Step 3: Configure DDR type */
mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
(sysinfo->ralat << 6) | (1 << 3);
/* Step 4: Configure delay while leaving reset */
mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
(sysinfo->rst_to_cke << 0);
/* Step 5: Configure DDR physical parameters (density and burst len) */
coladdr = lpddr2_cfg->coladdr;
if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr += 4;
else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
coladdr += 1;
mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
(coladdr - 9) << 20 | /* COL */
(0 << 19) | /* Burst Length = 4 for LPDDR2 */
(sysinfo->dsize << 16); /* DDR data bus size */
/* Step 6: Perform ZQ calibration */
val = 0xa1390003; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = val;
/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init LPDDR2 devices */
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR63: reset */
mmdc0->mdscr = MR(63, 0, 3, cs);
/* MR10: calibration,
* 0xff is calibration command after intilization.
*/
val = 0xA | (0xff << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR1 */
val = 0x1 | (0x82 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR2 */
val = 0x2 | (0x04 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR3 */
val = 0x3 | (0x02 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
}
/* Step 10: Power down control and self-refresh */
mmdc0->mdpdc = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */
1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 |
(tcksre & 0x7);
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
val = 0xa1310003;
mmdc0->mpzqhwctrl = val;
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
(3 << 11); /* REFR: Refresh Rate - 4 refreshes */
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = 0x00000000;
/* wait for auto-ZQ calibration to complete */
mdelay(1);
}
void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
@ -312,7 +658,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
!is_cpu_type(MXC_CPU_MX6SL))
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
@ -355,8 +702,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
trfc = DIV_ROUND_UP(260000, clkper) - 1;
txs = DIV_ROUND_UP(270000, clkper) - 1;
trfc = DIV_ROUND_UP(300000, clkper) - 1;
txs = DIV_ROUND_UP(310000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;
@ -598,3 +945,17 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* wait for auto-ZQ calibration to complete */
mdelay(1);
}
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const void *ddr_cfg)
{
if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
} else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
} else {
puts("Unsupported ddr type\n");
hang();
}
}

6
arch/arm/cpu/armv7/vf610/generic.c
View File

@ -9,6 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@ -266,6 +267,11 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
u32 get_cpu_rev(void)
{
return MXC_CPU_VF610 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{

18
arch/arm/imx-common/iomux-v3.c
View File

@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
}
#endif
#ifdef CONFIG_IOMUX_LPSR
u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_LPSR_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
/* set daisy chain sel_input */
if (sel_input_ofs)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
#endif
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
#endif
#ifdef CONFIG_IOMUX_LPSR
if (lpsr == IOMUX_CONFIG_LPSR)
base = (void *)IOMUXC_BASE_ADDR;
#endif
}
/* configures a list of pads within declared with IOMUX_PADS macro */

7
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -4,6 +4,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#define MXC_CPU_MX23 0x23
#define MXC_CPU_MX25 0x25
#define MXC_CPU_MX27 0x27
#define MXC_CPU_MX28 0x28
#define MXC_CPU_MX31 0x31
#define MXC_CPU_MX35 0x35
#define MXC_CPU_MX51 0x51
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
@ -15,6 +21,7 @@
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define CS0_128 0
#define CS0_64M_CS1_64M 1

7
arch/arm/include/asm/arch-mx31/sys_proto.h
View File

@ -5,8 +5,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#ifndef _MX31_SYS_PROTO_H_
#define _MX31_SYS_PROTO_H_
#include <asm/imx-common/sys_proto.h>
struct mxc_weimcs {
u32 upper;
@ -16,5 +18,4 @@ struct mxc_weimcs {
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
int mxc_mmc_init(bd_t *bis);
u32 get_cpu_rev(void);
#endif

12
arch/arm/include/asm/arch-mx35/sys_proto.h
View File

@ -5,12 +5,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#ifndef _MX35_SYS_PROTO_H_
#define _MX35_SYS_PROTO_H_
u32 get_cpu_rev(void);
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
u32 row, u32 col, u32 dsize, u32 refresh);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
#include <asm/imx-common/sys_proto.h>
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
u32 col, u32 dsize, u32 refresh);
#endif

11
arch/arm/include/asm/arch-mx5/iomux-mx51.h
View File

@ -184,8 +184,19 @@ enum {
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DISP2_DAT6__FEC_TDAT1 = IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DISP2_DAT7__FEC_TDAT2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DISP2_DAT8__FEC_TDAT3 = IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2),
MX51_PAD_DISP2_DAT11__FEC_RXCLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2),
MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4),
MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4),
MX51_PAD_DISP2_DAT14__FEC_RDAT0 = IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4),
MX51_PAD_DISP2_DAT15__FEC_TDAT0 = IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5),
MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),

22
arch/arm/include/asm/arch-mx5/sys_proto.h
View File

@ -5,24 +5,4 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include "../arch-imx/cpu.h"
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
unsigned imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
#endif
#include <asm/imx-common/sys_proto.h>

2
arch/arm/include/asm/arch-mx6/clock.h
View File

@ -64,7 +64,7 @@ int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);

6
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
/* ENET2 for i.MX6SX/UL */
#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
#define BP_ANADIG_PFD_480_PFD3_FRAC 24

3
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -630,9 +630,10 @@ struct ocotp_regs {
u32 version;
u32 rsvd7[0xdb];
/* fuse banks */
struct fuse_bank {
u32 fuse_regs[0x20];
} bank[16];
} bank[0];
};
struct fuse_bank0_regs {

140
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View File

@ -19,13 +19,22 @@
#ifdef CONFIG_MX6UL
#include "mx6ul-ddr.h"
#else
#ifdef CONFIG_MX6SL
#include "mx6sl-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
enum {
DDR_TYPE_DDR3,
DDR_TYPE_LPDDR2,
};
/* MMDC P0/P1 Registers */
struct mmdc_p_regs {
u32 mdctl;
@ -40,30 +49,120 @@ struct mmdc_p_regs {
u32 res1[2];
u32 mdrwd;
u32 mdor;
u32 res2[3];
u32 mdmrr;
u32 mdcfg3lp;
u32 mdmr4;
u32 mdasp;
u32 res3[240];
u32 res2[239];
u32 maarcr;
u32 mapsr;
u32 res4[254];
u32 maexidr0;
u32 maexidr1;
u32 madpcr0;
u32 madpcr1;
u32 madpsr0;
u32 madpsr1;
u32 madpsr2;
u32 madpsr3;
u32 madpsr4;
u32 madpsr5;
u32 masbs0;
u32 masbs1;
u32 res3[2];
u32 magenp;
u32 res4[239];
u32 mpzqhwctrl;
u32 res5[2];
u32 mpzqswctrl;
u32 mpwlgcr;
u32 mpwldectrl0;
u32 mpwldectrl1;
u32 res6;
u32 mpwldlst;
u32 mpodtctrl;
u32 mprddqby0dl;
u32 mprddqby1dl;
u32 mprddqby2dl;
u32 mprddqby3dl;
u32 res7[4];
u32 mpwrdqby0dl;
u32 mpwrdqby1dl;
u32 mpwrdqby2dl;
u32 mpwrdqby3dl;
u32 mpdgctrl0;
u32 mpdgctrl1;
u32 res8;
u32 mpdgdlst0;
u32 mprddlctl;
u32 res9;
u32 mprddlst;
u32 mpwrdlctl;
u32 res10[25];
u32 mpwrdlst;
u32 mpsdctrl;
u32 mpzqlp2ctl;
u32 mprddlhwctl;
u32 mpwrdlhwctl;
u32 mprddlhwst0;
u32 mprddlhwst1;
u32 mpwrdlhwst0;
u32 mpwrdlhwst1;
u32 mpwlhwerr;
u32 mpdghwst0;
u32 mpdghwst1;
u32 mpdghwst2;
u32 mpdghwst3;
u32 mppdcmpr1;
u32 mppdcmpr2;
u32 mpswdar0;
u32 mpswdrdr0;
u32 mpswdrdr1;
u32 mpswdrdr2;
u32 mpswdrdr3;
u32 mpswdrdr4;
u32 mpswdrdr5;
u32 mpswdrdr6;
u32 mpswdrdr7;
u32 mpmur0;
u32 mpwrcadl;
u32 mpdccr;
};
#define MX6SL_IOM_DDR_BASE 0x020e0300
struct mx6sl_iomux_ddr_regs {
u32 dram_cas;
u32 dram_cs0_b;
u32 dram_cs1_b;
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_ras;
u32 dram_reset;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_sdwe_b;
};
#define MX6SL_IOM_GRP_BASE 0x020e0500
struct mx6sl_iomux_grp_regs {
u32 res1[43];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 grp_ddrpk;
u32 grp_ddrhys;
u32 grp_ddrmode;
u32 grp_b0ds;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
};
#define MX6UL_IOM_DDR_BASE 0x020e0200
@ -278,6 +377,21 @@ struct mx6_ddr3_cfg {
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
};
/* Device Information: Varies per LPDDR2 part number and speed grade */
struct mx6_lpddr2_cfg {
u16 mem_speed; /* ie 800 for LPDDR2-800 */
u8 density; /* chip density (Gb) (1,2,4,8) */
u8 width; /* bus width (bits) (4,8,16) */
u8 banks; /* number of banks */
u8 rowaddr; /* row address bits (11-16)*/
u8 coladdr; /* col address bits (9-12) */
u16 trcd_lp;
u16 trppb_lp;
u16 trpab_lp;
u16 trcmin; /* tRC min (ns*100) */
u16 trasmin; /* tRAS min (ns*100) */
};
/* System Information: Varies per board design, layout, and term choices */
struct mx6_ddr_sysinfo {
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
@ -293,6 +407,7 @@ struct mx6_ddr_sysinfo {
u8 rst_to_cke; /* Time from SDE enable to CKE rise */
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
};
/*
@ -320,6 +435,8 @@ struct mx6_mmdc_calibration {
/* write delay */
u32 p0_mpwrdlctl;
u32 p1_mpwrdlctl;
/* lpddr2 zq hw calibration */
u32 mpzqlp2ctl;
};
/* configure iomux (pinctl/padctl) */
@ -335,11 +452,14 @@ void mx6sx_dram_iocfg(unsigned width,
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *,
const struct mx6ul_iomux_grp_regs *);
void mx6sl_dram_iocfg(unsigned width,
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
const struct mx6_mmdc_calibration *,
const struct mx6_ddr3_cfg *);
const void *);
#endif /* CONFIG_SPL_BUILD */

45
arch/arm/include/asm/arch-mx6/mx6sl-ddr.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6SL_DDR_H__
#define __ASM_ARCH_MX6SL_DDR_H__
#ifndef CONFIG_MX6SL
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_CAS_B 0x020e0300
#define MX6_IOM_DRAM_CS0_B 0x020e0304
#define MX6_IOM_DRAM_CS1_B 0x020e0308
#define MX6_IOM_DRAM_DQM0 0x020e030c
#define MX6_IOM_DRAM_DQM1 0x020e0310
#define MX6_IOM_DRAM_DQM2 0x020e0314
#define MX6_IOM_DRAM_DQM3 0x020e0318
#define MX6_IOM_DRAM_RAS_B 0x020e031c
#define MX6_IOM_DRAM_RESET 0x020e0320
#define MX6_IOM_DRAM_SDBA0 0x020e0324
#define MX6_IOM_DRAM_SDBA1 0x020e0328
#define MX6_IOM_DRAM_SDBA2 0x020e032c
#define MX6_IOM_DRAM_SDCKE0 0x020e0330
#define MX6_IOM_DRAM_SDCKE1 0x020e0334
#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
#define MX6_IOM_DRAM_ODT0 0x020e033c
#define MX6_IOM_DRAM_ODT1 0x020e0340
#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
#define MX6_IOM_DRAM_SDWE_B 0x020e0354
#endif /*__ASM_ARCH_MX6SL_DDR_H__ */

45
arch/arm/include/asm/arch-mx6/sys_proto.h
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@ -5,47 +5,4 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/imx-common/regs-common.h>
#include "../arch-imx/cpu.h"
#define soc_rev() (get_cpu_rev() & 0xFF)
#define is_soc_rev(rev) (soc_rev() == rev)
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
u32 get_cpu_temp_grade(int *minc, int *maxc);
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12) & 0xff)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
#endif
#include <asm/imx-common/sys_proto.h>

12
arch/arm/include/asm/arch-mx7/gpio.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX7_GPIO_H
#define __ASM_ARCH_MX7_GPIO_H
#include <asm/imx-common/gpio.h>
#endif /* __ASM_ARCH_MX7_GPIO_H */

19
arch/arm/include/asm/arch-mx7/mx7-pins.h Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX7_PINS_H__
#define __ASM_ARCH_MX7_PINS_H__
#include <asm/imx-common/iomux-v3.h>
#if defined(CONFIG_MX7D)
#include "mx7d_pins.h"
#elif defined(CONFIG_MX7S)
#include "mx7s_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX7D */
#endif /*__ASM_ARCH_MX7_PINS_H__ */

1308
arch/arm/include/asm/arch-mx7/mx7d_pins.h Normal file
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File diff suppressed because it is too large Load Diff

14
arch/arm/include/asm/arch-mxs/sys_proto.h
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@ -7,18 +7,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SYS_PROTO_H__
#define __SYS_PROTO_H__
#ifndef __MXS_SYS_PROTO_H__
#define __MXS_SYS_PROTO_H__
#include <asm/imx-common/regs-common.h>
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
#include <asm/imx-common/sys_proto.h>
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));

32
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t;
#define NO_PAD_CTRL (1 << 17)
#ifdef CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
#define IOMUX_CONFIG_LPSR 0x8
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
#define PAD_CTL_SRE_FAST (0 << 2)
#define PAD_CTL_SRE_SLOW (0x1 << 2)
#define PAD_CTL_HYS (0x1 << 3)
#define PAD_CTL_PUE (0x1 << 4)
#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
#else
#ifdef CONFIG_MX6
#define PAD_CTL_HYS (1 << 16)
@ -173,6 +203,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_SRE_SLOW (0 << 0)
#define PAD_CTL_SRE_FAST (1 << 0)
#endif
#define IOMUX_CONFIG_SION 0x10
#define GPIO_PIN_MASK 0x1f

46
arch/arm/include/asm/imx-common/sys_proto.h Normal file
View File

@ -0,0 +1,46 @@
/*
* (C) Copyright 2009
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/imx-common/regs-common.h>
#include <common.h>
#include "../arch-imx/cpu.h"
#define soc_rev() (get_cpu_rev() & 0xFF)
#define is_soc_rev(rev) (soc_rev() == rev)
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12) & 0xff)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
u32 get_cpu_temp_grade(int *minc, int *maxc);
const char *get_imx_type(u32 imxtype);
u32 imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
#endif

13
board/aristainetos/Kconfig
View File

@ -23,3 +23,16 @@ config SYS_CONFIG_NAME
default "aristainetos2"
endif
if TARGET_ARISTAINETOS2B
config SYS_BOARD
default "aristainetos"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "aristainetos2b"
endif

2
board/aristainetos/aristainetos-v1.c
View File

@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
ret = enable_fec_anatop_clock(ENET_50MHZ);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;

57
board/aristainetos/aristainetos-v2.c
View File

@ -42,8 +42,16 @@
#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */
#define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
#if (CONFIG_SYS_BOARD_VERSION == 2)
/* 4.3 display controller */
#define ECSPI1_CS0 IMX_GPIO_NR(4, 9)
#define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
#elif (CONFIG_SYS_BOARD_VERSION == 3)
#define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */
/* 4.3 display controller */
#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
#endif
#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13)
#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
@ -103,7 +111,11 @@ iomux_v3_cfg_t const gpio_pads[] = {
/* LED yellow */
MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED red */
#if (CONFIG_SYS_BOARD_VERSION == 2)
MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
#elif (CONFIG_SYS_BOARD_VERSION == 3)
MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#endif
/* LED green */
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED blue */
@ -170,7 +182,12 @@ static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
#if (CONFIG_SYS_BOARD_VERSION == 2)
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
#elif (CONFIG_SYS_BOARD_VERSION == 3)
MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
#endif
};
static void setup_iomux_enet(void)
@ -178,6 +195,7 @@ static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
#if (CONFIG_SYS_BOARD_VERSION == 2)
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
@ -185,13 +203,13 @@ iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#endif
static iomux_v3_cfg_t const display_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
MX6_PAD_DI0_PIN4__GPIO4_IO20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
@ -221,11 +239,17 @@ static iomux_v3_cfg_t const display_pads[] = {
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
#if (CONFIG_SYS_BOARD_VERSION == 2)
return IMX_GPIO_NR(5, 2);
if (bus == 0 && cs == 0)
return IMX_GPIO_NR(4, 9);
#elif (CONFIG_SYS_BOARD_VERSION == 3)
return ECSPI1_CS0;
if (bus == 0 && cs == 1)
return ECSPI1_CS1;
#endif
return -1;
}
@ -234,15 +258,22 @@ static void setup_spi(void)
int i;
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#if (CONFIG_SYS_BOARD_VERSION == 2)
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
#endif
for (i = 0; i < 4; i++)
enable_spi_clk(true, i);
gpio_direction_output(ECSPI1_CS0, 1);
#if (CONFIG_SYS_BOARD_VERSION == 2)
gpio_direction_output(ECSPI4_CS1, 0);
/* set cs0 to high (second device on spi bus #4) */
gpio_direction_output(ECSPI4_CS0, 1);
#elif (CONFIG_SYS_BOARD_VERSION == 3)
gpio_direction_output(ECSPI1_CS1, 1);
#endif
}
static void setup_iomux_uart(void)
@ -573,6 +604,7 @@ static void setup_board_gpio(void)
gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
/* switch off Status LEDs */
#if (CONFIG_SYS_BOARD_VERSION == 2)
gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
@ -581,11 +613,21 @@ static void setup_board_gpio(void)
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
#elif (CONFIG_SYS_BOARD_VERSION == 3)
gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
#endif
}
static void setup_board_spi(void)
{
/* enable spi bus #2 SS drivers */
/* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
}
@ -620,8 +662,9 @@ int board_late_init(void)
/* if we have the lg panel, we can initialze it now */
if (panel)
if (!strcmp(panel, displays[1].mode.name))
lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0);
lg4573_spi_startup(CONFIG_LG4573_BUS,
CONFIG_LG4573_CS,
10000000, SPI_MODE_0);
return 0;
}

19
board/aristainetos/aristainetos.c
View File

@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_SYS_BOARD_VERSION == 1)
#include "./aristainetos-v1.c"
#elif (CONFIG_SYS_BOARD_VERSION == 2)
#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
#include "./aristainetos-v2.c"
#endif
@ -163,18 +163,18 @@ struct display_info_t const displays[] = {
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 33246,
.pixclock = 30066,
.left_margin = 88,
.right_margin = 88,
.upper_margin = 10,
.lower_margin = 10,
.upper_margin = 20,
.lower_margin = 20,
.hsync_len = 80,
.vsync_len = 25,
.sync = 0,
.vsync_len = 5,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
}
#if (CONFIG_SYS_BOARD_VERSION == 2)
#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
, {
.bus = -1,
.addr = 0,
@ -183,7 +183,7 @@ struct display_info_t const displays[] = {
.enable = enable_spi_display,
.mode = {
.name = "lg4573",
.refresh = 60,
.refresh = 57,
.xres = 480,
.yres = 800,
.pixclock = 37037,
@ -214,9 +214,6 @@ iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),

2
board/barco/platinum/platinum_picon.c
View File

@ -148,7 +148,7 @@ int platinum_setup_enet(void)
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(ENET_50MHZ);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int platinum_setup_i2c(void)

1
board/barco/platinum/spl_picon.c
View File

@ -137,6 +137,7 @@ static void spl_dram_init(int width)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);

1
board/barco/platinum/spl_titanium.c
View File

@ -140,6 +140,7 @@ static void spl_dram_init(int width)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);

2
board/boundary/nitrogen6x/MAINTAINERS
View File

@ -1,5 +1,5 @@
NITROGEN6X BOARD
M: Eric Nelson <eric.nelson@boundarydevices.com>
M: Troy Kisky <troy.kisky@boundarydevices.com>
S: Maintained
F: board/boundary/nitrogen6x/
F: include/configs/nitrogen6x.h

13
board/compulab/cm_fx6/cm_fx6.c
View File

@ -14,6 +14,7 @@
#include <miiphy.h>
#include <netdev.h>
#include <errno.h>
#include <usb.h>
#include <fdt_support.h>
#include <sata.h>
#include <splash.h>
@ -330,6 +331,11 @@ static int cm_fx6_setup_usb_otg(void)
return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
}
int board_usb_phy_mode(int port)
{
return USB_INIT_HOST;
}
int board_ehci_hcd_init(int port)
{
int ret;
@ -620,6 +626,13 @@ int checkboard(void)
return 0;
}
int misc_init_r(void)
{
cl_print_pcb_info();
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;

207
board/congatec/cgtqmx6eval/cgtqmx6eval.c
View File

@ -27,6 +27,10 @@
#include <power/pfuze100_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <micrel.h>
DECLARE_GLOBAL_DATA_PTR;
@ -43,6 +47,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@ -98,6 +107,51 @@ static iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t enet_pads_ksz9031[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t enet_pads_ar8035[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
@ -169,6 +223,159 @@ int power_init_board(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
struct phy_device *phydev;
struct mii_dev *bus;
unsigned short id1, id2;
int ret;
iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 |
MUX_PAD_CTRL(NO_PAD_CTRL);
/* check whether KSZ9031 or AR8035 has to be configured */
imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035,
ARRAY_SIZE(enet_pads_ar8035));
imx_iomux_v3_setup_pad(enet_reset);
/* phy reset */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
udelay(2000);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
udelay(500);
bus = fec_get_miibus(IMX_FEC_BASE, -1);
if (!bus)
return -EINVAL;
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("Error: phy device not found.\n");
ret = -ENODEV;
goto free_bus;
}
/* get the PHY id */
id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
/* re-configure for Micrel KSZ9031 */
printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
phydev->addr);
/* phy reset: gpio3-23 */
gpio_set_value(IMX_GPIO_NR(3, 23), 0);
gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
gpio_set_value(IMX_GPIO_NR(6, 25), 1);
gpio_set_value(IMX_GPIO_NR(6, 27), 1);
gpio_set_value(IMX_GPIO_NR(6, 28), 1);
gpio_set_value(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031,
ARRAY_SIZE(enet_pads_ksz9031));
gpio_set_value(IMX_GPIO_NR(6, 24), 1);
udelay(500);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031,
ARRAY_SIZE(enet_pads_final_ksz9031));
} else if ((id1 == 0x004d) && (id2 == 0xd072)) {
/* configure Atheros AR8035 - actually nothing to do */
printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
phydev->addr);
} else {
printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
ret = -EINVAL;
goto free_phydev;
}
ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
if (ret)
goto free_phydev;
return 0;
free_phydev:
free(phydev);
free_bus:
free(bus);
return ret;
}
int mx6_rgmii_rework(struct phy_device *phydev)
{
unsigned short id1, id2;
unsigned short val;
/* check whether KSZ9031 or AR8035 has to be configured */
id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
/* finalize phy configuration for Micrel KSZ9031 */
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
/* fix KSZ9031 link up issue */
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
}
if ((id1 == 0x004d) && (id2 == 0xd072)) {
/* enable AR8035 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
val &= 0xfe63;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
/* disable hibernation */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
}
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static void setup_iomux_uart(void)
{

2
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View File

@ -361,7 +361,7 @@ static void setup_fec(void)
* select ENET MAC0 TX clock from PLL
*/
imx_iomux_set_gpr_register(5, 9, 1, 1);
enable_fec_anatop_clock(ENET_125MHZ);
enable_fec_anatop_clock(0, ENET_125MHZ);
}
setup_iomux_enet();

1
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -824,6 +824,7 @@ static void spl_dram_init(void)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);

166
board/freescale/mx6slevk/mx6slevk.c
View File

@ -8,7 +8,9 @@
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
@ -190,6 +192,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int i, ret;
/*
@ -234,6 +237,44 @@ int board_mmc_init(bd_t *bis)
}
return 0;
#else
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
/* Boot from USDHC */
port = (val >> 11) & 0x3;
switch (port) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#ifdef CONFIG_SYS_I2C_MXC
@ -279,7 +320,7 @@ static int setup_fec(void)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
return enable_fec_anatop_clock(ENET_50MHZ);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif
@ -361,3 +402,126 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <libfdt.h>
const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdqs0 = 0x00003030,
.dram_sdqs1 = 0x00003030,
.dram_sdqs2 = 0x00003030,
.dram_sdqs3 = 0x00003030,
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_dqm2 = 0x00000030,
.dram_dqm3 = 0x00000030,
.dram_cas = 0x00000030,
.dram_ras = 0x00000030,
.dram_sdclk_0 = 0x00000028,
.dram_reset = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_odt0 = 0x00000008,
.dram_odt1 = 0x00000008,
};
const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_addds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x00080000,
};
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpdgctrl0 = 0x20000000,
.p0_mpdgctrl1 = 0x00000000,
.p0_mprddlctl = 0x4241444a,
.p0_mpwrdlctl = 0x3030312b,
.mpzqlp2ctl = 0x1b4700c7,
};
static struct mx6_lpddr2_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 32,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.trcd_lp = 2000,
.trppb_lp = 2000,
.trpab_lp = 2250,
.trasmin = 4200,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0x00260324, &ccm->cbcmr);
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
.dsize = mem_ddr.width / 32,
.cs_density = 20,
.ncs = 2,
.cs1_mirror = 0,
.walat = 0,
.ralat = 2,
.mif3_mode = 3,
.bi_on = 1,
.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
.rtt_nom = 0,
.sde_to_rst = 0, /* LPDDR2 does not need this field */
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
.ddr_type = DDR_TYPE_LPDDR2,
};
mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void reset_cpu(ulong addr)
{
}
#endif

3
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -170,7 +170,7 @@ static int setup_fec(void)
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(ENET_125MHZ);
return enable_fec_anatop_clock(0, ENET_125MHZ);
}
int board_eth_init(bd_t *bis)
@ -566,6 +566,7 @@ static void spl_dram_init(void)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);

111
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
View File

@ -19,8 +19,10 @@
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-fsl.h>
@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define IOX_SDI IMX_GPIO_NR(5, 10)
#define IOX_STCP IMX_GPIO_NR(5, 7)
#define IOX_SHCP IMX_GPIO_NR(5, 11)
@ -457,6 +471,98 @@ int board_ehci_hcd_init(int port)
}
#endif
#ifdef CONFIG_FEC_MXC
/*
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
* be used for ENET1 or ENET2, cannot be used for both.
*/
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
{
if (fec_id == 0)
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
}
int board_eth_init(bd_t *bis)
{
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
}
static int setup_fec(int fec_id)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (fec_id == 0) {
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
/*
* Use 50M anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
}
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
@ -477,6 +583,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
#ifdef CONFIG_FEC_MXC
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
@ -598,6 +708,7 @@ static void spl_dram_init(void)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);

1
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -365,6 +365,7 @@ static void spl_dram_init(int width, int size_mb, int board_model)
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.pd_fast_exit = 1, /* enable precharge power-down fast exit */
.ddr_type = DDR_TYPE_DDR3,
};
/*

3
board/solidrun/mx6cuboxi/mx6cuboxi.c
View File

@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
struct mii_dev *bus;
struct phy_device *phydev;
int ret = enable_fec_anatop_clock(ENET_25MHZ);
int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
if (ret)
return ret;
@ -615,6 +615,7 @@ static void spl_dram_init(int width)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))

9
board/tbs/tbs2910/Kconfig
View File

@ -6,10 +6,13 @@ config SYS_BOARD
config SYS_VENDOR
default "tbs"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "tbs2910"
config MX6Q
default y
config IMX_CONFIG
default "board/boundary/nitrogen6x/nitrogen6q2g.cfg"
endif

15
board/technologic/ts4800/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_TS4800
config SYS_BOARD
default "ts4800"
config SYS_VENDOR
default "technologic"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "ts4800"
endif

6
board/technologic/ts4800/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
TS4800 BOARD
M: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
S: Maintained
F: board/ts/ts4800/
F: include/configs/ts4800.h
F: configs/ts4800_defconfig

7
board/technologic/ts4800/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2015 Savoir-faire Linux
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ts4800.o

257
board/technologic/ts4800/ts4800.c Normal file
View File

@ -0,0 +1,257 @@
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*
* Derived from MX51EVK code by
* Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/mx5_video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mc13892.h>
#include <malloc.h>
#include <netdev.h>
#include <phy.h>
#include "ts4800.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
PAD_CTL_HYS |
PAD_CTL_PUS_22K_UP |
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
MX51_PAD_EIM_EB3__FEC_RDATA1,
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
MX51_PAD_EIM_CS3__FEC_RDATA3,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_EIM_CS4__FEC_RX_ER,
/* PAD used on TS4800 */
MX51_PAD_DI2_PIN2__FEC_MDC,
MX51_PAD_DISP2_DAT14__FEC_RDAT0,
MX51_PAD_DISP2_DAT10__FEC_COL,
MX51_PAD_DISP2_DAT11__FEC_RXCLK,
MX51_PAD_DISP2_DAT15__FEC_TDAT0,
MX51_PAD_DISP2_DAT6__FEC_TDAT1,
MX51_PAD_DISP2_DAT7__FEC_TDAT2,
MX51_PAD_DISP2_DAT8__FEC_TDAT3,
MX51_PAD_DISP2_DAT9__FEC_TX_EN,
MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
MX51_PAD_DISP2_DAT12__FEC_RX_DV,
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 0));
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
else
ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
return ret;
}
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
};
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
/*
* Read the MAC address from FEC's registers PALR PAUR.
* User is supposed to configure these registers when MAC address is known
* from another source (fuse), but on TS4800, MAC address is not fused and
* the bootrom configure these registers on startup.
*/
static int fec_get_mac_from_register(uint32_t base_addr)
{
unsigned char ethaddr[6];
u32 reg_mac[2];
int i;
reg_mac[0] = in_be32(base_addr + 0xE4);
reg_mac[1] = in_be32(base_addr + 0xE8);
for(i = 0; i < 6; i++)
ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
if (is_valid_ethaddr(ethaddr)) {
eth_setenv_enetaddr("ethaddr", ethaddr);
return 0;
}
return -1;
}
#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
int board_eth_init(bd_t *bd)
{
int dev_id = -1;
int phy_id = 0xFF;
uint32_t addr = IMX_FEC_BASE;
uint32_t base_mii;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
/* reset FEC phy */
imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
mdelay(1);
gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
mdelay(1);
base_mii = addr;
debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
bus = fec_get_miibus(base_mii, dev_id);
if (!bus)
return -ENOMEM;
phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
if (!phydev) {
free(bus);
return -ENOMEM;
}
if (fec_get_mac_from_register(addr))
printf("eth_init: failed to get MAC address\n");
ret = fec_probe(bd, dev_id, addr, bus, phydev);
if (ret) {
free(phydev);
free(bus);
}
return ret;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int checkboard(void)
{
puts("Board: TS4800\n");
return 0;
}
void hw_watchdog_reset(void)
{
struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
/* feed the watchdog for another 10s */
writew(0x2, &wtd->feed);
}
void hw_watchdog_init(void)
{
return;
}

16
board/technologic/ts4800/ts4800.h Normal file
View File

@ -0,0 +1,16 @@
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TS4800_H
#define _TS4800_H
#define TS4800_SYSCON_BASE 0xb0010000
struct ts4800_wtd_regs {
u16 feed;
};
#endif

1
board/tqc/tqma6/tqma6.c
View File

@ -25,6 +25,7 @@
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
#include <spi_flash.h>
#include "tqma6_bb.h"

55
board/udoo/1066mhz_4x256mx16.cfg
View File

@ -1,55 +0,0 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

2
board/udoo/MAINTAINERS
View File

@ -3,4 +3,4 @@ M: Fabio Estevam <fabio.estevam@freescale.com>
S: Maintained
F: board/udoo/
F: include/configs/udoo.h
F: configs/udoo_quad_defconfig
F: configs/udoo_defconfig

2
board/udoo/Makefile
View File

@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := udoo.o
obj-y := udoo.o udoo_spl.o

32
board/udoo/clocks.cfg
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

87
board/udoo/ddr-setup.cfg
View File

@ -1,87 +0,0 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* DDR3 settings
* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
* memory bus width: 64 bits x16/x32/x64
* MX6DL ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 64 bits x16/x32/x64
* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 32 bits x16/x32
*/
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
/* (differential input) */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
/* (differential input) */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
/* disable ddr pullups */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* Read data DQ Byte0-3 delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333

95
board/udoo/udoo.c
View File

@ -42,28 +42,28 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19,
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
};
int mx6_rgmii_rework(struct phy_device *phydev)
@ -96,43 +96,43 @@ int mx6_rgmii_rework(struct phy_device *phydev)
}
static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* RGMII reset */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* Ethernet power supply */
MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
SETUP_IOMUX_PADS(enet_pads1);
udelay(20);
gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
@ -156,17 +156,17 @@ static void setup_iomux_enet(void)
gpio_free(IMX_GPIO_NR(6, 28));
gpio_free(IMX_GPIO_NR(6, 29));
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
SETUP_IOMUX_PADS(enet_pads2);
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
SETUP_IOMUX_PADS(uart2_pads);
}
static void setup_iomux_wdog(void)
{
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
SETUP_IOMUX_PADS(wdog_pads);
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
gpio_direction_input(WDT_TRG);
@ -212,7 +212,7 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
@ -242,14 +242,29 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_CMD_SATA
setup_sata();
if (is_cpu_type(MXC_CPU_MX6Q))
setup_sata();
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_cpu_type(MXC_CPU_MX6Q))
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
#endif
return 0;
}
int checkboard(void)
{
puts("Board: Udoo\n");
if (is_cpu_type(MXC_CPU_MX6Q))
puts("Board: Udoo Quad\n");
else
puts("Board: Udoo DualLite\n");
return 0;
}

29
board/udoo/udoo.cfg
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "1066mhz_4x256mx16.cfg"
#include "clocks.cfg"

271
board/udoo/udoo_spl.c Normal file
View File

@ -0,0 +1,271 @@
/*
* Copyright (C) 2015 Udoo
* Author: Tungyi Lin <tungyilin1127@gmail.com>
* Richard Hu <hakahu@gmail.com>
* Based on board/wandboard/spl.c
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
.dram_cas = IMX6DQ_DRIVE_STRENGTH,
.dram_ras = IMX6DQ_DRIVE_STRENGTH,
.dram_reset = IMX6DQ_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
};
/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6DQ_DRIVE_STRENGTH,
.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
/* quad = 1066, duallite = 800 */
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
.p0_mpwldectrl0 = 0x00350035,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x00010001,
.p1_mpwldectrl1 = 0x00010001,
.p0_mpdgctrl0 = 0x43510360,
.p0_mpdgctrl1 = 0x0342033F,
.p1_mpdgctrl0 = 0x033F033F,
.p1_mpdgctrl1 = 0x03290266,
.p0_mprddlctl = 0x4B3E4141,
.p1_mprddlctl = 0x47413B4A,
.p0_mpwrdlctl = 0x42404843,
.p1_mpwrdlctl = 0x4C3F4C45,
};
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
.p0_mpwldectrl0 = 0x002F0038,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x001F001F,
.p1_mpwldectrl1 = 0x001F001F,
.p0_mpdgctrl0 = 0x425C0251,
.p0_mpdgctrl1 = 0x021B021E,
.p1_mpdgctrl0 = 0x021B021E,
.p1_mpdgctrl1 = 0x01730200,
.p0_mprddlctl = 0x45474C45,
.p1_mprddlctl = 0x44464744,
.p0_mpwrdlctl = 0x3F3F3336,
.p1_mpwrdlctl = 0x32383630,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_qdl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
/* quad = 2, duallite = 1 */
.rtt_nom = 2,
/* quad = 2, duallite = 1 */
.rtt_wr = 2,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* set the default clock gate to save power */
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000FF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6DL)) {
mt41k128m16jt_125.mem_speed = 800;
mem_qdl.rtt_nom = 1;
mem_qdl.rtt_wr = 1;
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
} else if (is_cpu_type(MXC_CPU_MX6Q)) {
mt41k128m16jt_125.mem_speed = 1066;
mem_qdl.rtt_nom = 2;
mem_qdl.rtt_wr = 2;
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
}
udelay(100);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

1
configs/aristainetos2_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set

7
configs/aristainetos2b_defconfig Normal file
View File

@ -0,0 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS2B=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y

1
configs/aristainetos_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set

1
configs/cgtqmx6qeval_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set

2
configs/cm_fx6_defconfig
View File

@ -28,5 +28,5 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_SYS_PROMPT="CM-FX6 # "
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

1
configs/gwventana_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y

1
configs/marsboard_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
# CONFIG_CMD_IMLS is not set

1
configs/mx6cuboxi_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6CUBOXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"

1
configs/mx6dlarm2_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set

1
configs/mx6dlarm2_lpddr2_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
# CONFIG_CMD_IMLS is not set

1
configs/mx6dlsabreauto_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set

1
configs/mx6dlsabresd_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set

1
configs/mx6qarm2_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set

1
configs/mx6qarm2_lpddr2_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
# CONFIG_CMD_IMLS is not set

1
configs/mx6qpsabreauto_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
CONFIG_SPI_FLASH=y

1
configs/mx6qsabreauto_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set

1
configs/mx6qsabrelite_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
# CONFIG_CMD_IMLS is not set

1
configs/mx6qsabresd_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set

1
configs/mx6sabresd_spl_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"

1
configs/mx6slevk_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
# CONFIG_CMD_IMLS is not set

1
configs/mx6slevk_spinor_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
# CONFIG_CMD_IMLS is not set

8
configs/mx6slevk_spl_defconfig Normal file
View File

@ -0,0 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_THERMAL=y

1
configs/mx6sxsabresd_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
# CONFIG_CMD_IMLS is not set

1
configs/mx6sxsabresd_spl_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"

8
configs/mx6ul_14x14_evk_defconfig
View File

@ -1,4 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_ARCH_MX6=y
CONFIG_CMD_NET=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_TARGET_MX6UL_14X14_EVK=y

1
configs/nitrogen6dl2g_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set

1
configs/nitrogen6dl_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set

1
configs/nitrogen6q2g_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set

1
configs/nitrogen6q_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set

1
configs/nitrogen6s1g_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set

1
configs/nitrogen6s_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
# CONFIG_CMD_IMLS is not set

1
configs/novena_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"

1
configs/ot1200_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_OT1200=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set

1
configs/ot1200_spl_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_OT1200=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"

1
configs/platinum_picon_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"

1
configs/platinum_titanium_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PLATINUM_TITANIUM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"

1
configs/riotboard_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
# CONFIG_CMD_IMLS is not set

2
configs/tbs2910_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TBS2910=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y

1
configs/tqma6s_wru4_mmc_defconfig
View File

@ -7,5 +7,4 @@ CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
CONFIG_SPI_FLASH=y
CONFIG_PCA9551_LED=y

4
configs/ts4800_defconfig Normal file
View File

@ -0,0 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_TS4800=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set

7
configs/udoo_defconfig Normal file
View File

@ -0,0 +1,7 @@
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_TARGET_UDOO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"

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