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armv8/ls1043a: Implement workaround for PEX erratum A009929

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Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Mingkai Hu 2015-12-07 16:58:54 +08:00 committed by York Sun
parent 2949ae5212
commit 0d6faf2bd0
3 changed files with 18 additions and 0 deletions
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16
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -197,6 +197,19 @@ int sata_init(void)
}
#endif
static void erratum_a009929(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
rstrqmr1 |= 0x00000400;
gur_out32(&gur->rstrqmr1, rstrqmr1);
writel(0x01000000, dcsr_cop_ccp);
#endif
}
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@ -216,6 +229,9 @@ void fsl_lsch2_early_init_f(void)
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
/* Erratum */
erratum_a009929();
}
#endif

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -166,6 +166,7 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_ERRATUM_A009929
#else
#error SoC not defined
#endif

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -12,6 +12,7 @@
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)