powerpc: ppc4xx: remove alpr support
This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
c4620350c4
commit
0d2fc81133
@ -140,9 +140,6 @@ config TARGET_MIP405
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config TARGET_PIP405
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bool "Support PIP405"
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config TARGET_ALPR
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bool "Support alpr"
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config TARGET_P3P440
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bool "Support p3p440"
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@ -197,7 +194,6 @@ source "board/mosaixtech/icon/Kconfig"
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source "board/mpl/mip405/Kconfig"
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source "board/mpl/pip405/Kconfig"
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source "board/pcs440ep/Kconfig"
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source "board/prodrive/alpr/Kconfig"
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source "board/prodrive/p3p440/Kconfig"
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source "board/sbc405/Kconfig"
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source "board/t3corp/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_ALPR
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config SYS_BOARD
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default "alpr"
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config SYS_VENDOR
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default "prodrive"
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config SYS_CONFIG_NAME
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default "alpr"
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endif
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@ -1,6 +0,0 @@
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ALPR BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/prodrive/alpr/
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F: include/configs/alpr.h
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F: configs/alpr_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = alpr.o fpga.o nand.o
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extra-y += init.o
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@ -1,215 +0,0 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <asm/ppc4xx-emac.h>
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#include <miiphy.h>
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#include <asm/processor.h>
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#include <asm/4xx_pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int alpr_fpga_init(void);
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG
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*-------------------------------------------------------------------------*/
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mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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/*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC1ER, 0x00000000); /* disable all */
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mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (UIC1PR, 0xfffffe03); /* per manual */
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mtdcr (UIC1TR, 0x01c00000); /* per manual */
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mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC2ER, 0x00000000); /* disable all */
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mtdcr (UIC2CR, 0x00000000); /* all non-critical */
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mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
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mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC3ER, 0x00000000); /* disable all */
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mtdcr (UIC3CR, 0x00000000); /* all non-critical */
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mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC0SR, 0xfc000000); /* clear all */
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mtdcr (UIC0ER, 0x00000000); /* disable all */
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mtdcr (UIC0CR, 0x00000000); /* all non-critical */
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mtdcr (UIC0PR, 0xfc000000); /* */
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mtdcr (UIC0TR, 0x00000000); /* */
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mtdcr (UIC0VR, 0x00000001); /* */
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/* Setup shutdown/SSD empty interrupt as inputs */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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/* Setup GPIO/IRQ multiplexing */
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mtsdr(SDR0_PFC0, 0x01a33e00);
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return 0;
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}
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int last_stage_init(void)
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{
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unsigned short reg;
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/*
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* Configure LED's of both Marvell 88E1111 PHY's
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*
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* This has to be done after the 4xx ethernet driver is loaded,
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* so "last_stage_init()" is the right place.
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*/
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miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
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miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
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return 0;
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}
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static int board_rev(void)
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{
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/* Setup as input */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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return (in32(GPIO0_IR) >> 16) & 0x3;
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}
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int checkboard (void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf ("Board: ALPR");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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printf(" (Rev. %d)\n", board_rev());
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return (0);
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}
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#if defined(CONFIG_PCI)
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/*
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* Override weak pci_pre_init()
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*/
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int pci_pre_init(struct pci_controller *hose)
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{
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if (__pci_pre_init(hose) == 0)
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return 0;
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/* FPGA Init */
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alpr_fpga_init();
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return 1;
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}
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/*************************************************************************
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* Override weak is_pci_host()
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
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return;
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}
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}
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int is_pci_host(struct pci_controller *hose)
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{
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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| PowerPC440 PCI Master configuration.
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| Map PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r( PCIL0_POM0SA, 0 ); /* disable */
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out32r( PCIL0_POM1SA, 0 ); /* disable */
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out32r( PCIL0_POM2SA, 0 ); /* disable */
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out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
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@ -1,16 +0,0 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif
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@ -1,239 +0,0 @@
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/*
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Altera FPGA configuration support for the ALPR computer from prodrive
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*/
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#include <common.h>
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#include <altera.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/ppc440.h>
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt, args...) printf(fmt , ##args)
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#else
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#define PRINTF(fmt, args...)
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#endif
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static unsigned long regval;
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#define SET_GPIO_REG_0(reg, bit) do { \
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regval = in32(reg); \
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regval &= ~(0x80000000 >> bit); \
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out32(reg, regval); \
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} while (0)
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#define SET_GPIO_REG_1(reg, bit) do { \
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regval = in32(reg); \
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regval |= (0x80000000 >> bit); \
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out32(reg, regval); \
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} while (0)
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#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
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#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
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#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
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#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
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#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
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#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
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#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
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#define SET_FPGA(data) out32(GPIO0_OR, data)
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#define FPGA_WRITE_1 do { \
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SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \
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} while (0)
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#define FPGA_WRITE_0 do { \
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SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \
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} while (0)
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/* Plattforminitializations */
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/* Here we have to set the FPGA Chain */
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/* PROGRAM_PROG_EN = HIGH */
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/* PROGRAM_SEL_DPR = LOW */
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int fpga_pre_fn(int cookie)
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{
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/* Enable the FPGA Chain */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
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SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
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/* initialize the GPIO Pins */
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/* output */
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SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
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/* output */
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SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
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/* First we set STATUS to 0 then as an input */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
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/* output */
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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/* input */
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SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
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SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
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/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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return FPGA_SUCCESS;
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}
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/* Set the state of CONFIG Pin */
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int fpga_config_fn(int assert_config, int flush, int cookie)
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{
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if (assert_config)
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SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
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else
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
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return FPGA_SUCCESS;
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}
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/* Returns the state of STATUS Pin */
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int fpga_status_fn(int cookie)
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{
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unsigned long reg;
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reg = in32(GPIO0_IR);
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if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
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PRINTF("STATUS = HIGH\n");
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return FPGA_FAIL;
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}
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PRINTF("STATUS = LOW\n");
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return FPGA_SUCCESS;
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}
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/* Returns the state of CONF_DONE Pin */
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int fpga_done_fn(int cookie)
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{
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unsigned long reg;
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reg = in32(GPIO0_IR);
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if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
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PRINTF("CONF_DON = HIGH\n");
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return FPGA_FAIL;
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}
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PRINTF("CONF_DON = LOW\n");
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return FPGA_SUCCESS;
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}
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/* writes the complete buffer to the FPGA
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writing the complete buffer in one function is much faster,
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then calling it for every bit */
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int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
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{
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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unsigned char val = 0;
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int i;
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int len_40 = len / 40;
|
||||
|
||||
while (bytecount < len) {
|
||||
val = data[bytecount++];
|
||||
i = 8;
|
||||
do {
|
||||
if (val & 0x01)
|
||||
FPGA_WRITE_1;
|
||||
else
|
||||
FPGA_WRITE_0;
|
||||
|
||||
val >>= 1;
|
||||
i--;
|
||||
} while (i > 0);
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
if (bytecount % len_40 == 0) {
|
||||
putc('.'); /* let them know we are alive */
|
||||
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
|
||||
if (ctrlc())
|
||||
return FPGA_FAIL;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming is aborted */
|
||||
int fpga_abort_fn(int cookie)
|
||||
{
|
||||
SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming was succesful */
|
||||
int fpga_post_fn(int cookie)
|
||||
{
|
||||
return fpga_abort_fn(cookie);
|
||||
}
|
||||
|
||||
/* Note that these are pointers to code that is in Flash. They will be
|
||||
* relocated at runtime.
|
||||
*/
|
||||
Altera_CYC2_Passive_Serial_fns fpga_fns = {
|
||||
fpga_pre_fn,
|
||||
fpga_config_fn,
|
||||
fpga_status_fn,
|
||||
fpga_done_fn,
|
||||
fpga_write_fn,
|
||||
fpga_abort_fn,
|
||||
fpga_post_fn
|
||||
};
|
||||
|
||||
Altera_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
{Altera_CYC2,
|
||||
passive_serial,
|
||||
Altera_EP2C35_SIZE,
|
||||
(void *) &fpga_fns,
|
||||
NULL,
|
||||
0}
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||
*/
|
||||
int alpr_fpga_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__);
|
||||
fpga_init();
|
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
|
||||
PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
|
||||
fpga_add(fpga_altera, &fpga[i]);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1,53 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm-offsets.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
|
||||
#else
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
|
||||
#endif
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
||||
|
||||
/* PCI */
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
|
||||
|
||||
/* NAND */
|
||||
tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
|
||||
tlbtab_end
|
||||
@ -1,124 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <nand.h>
|
||||
|
||||
struct alpr_ndfc_regs {
|
||||
u8 cmd[4];
|
||||
u8 addr_wait;
|
||||
u8 term;
|
||||
u8 dummy;
|
||||
u8 dummy2;
|
||||
u8 data;
|
||||
};
|
||||
|
||||
static u8 hwctl;
|
||||
static struct alpr_ndfc_regs *alpr_ndfc = NULL;
|
||||
|
||||
#define readb(addr) (u8)(*(volatile u8 *)(addr))
|
||||
#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
|
||||
|
||||
/*
|
||||
* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
|
||||
* the NAND devices. The NDFC has command, address and data registers that
|
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the
|
||||
* hwcontrol function to save the configuration in a global variable.
|
||||
* We can then use this information in the read and write functions to
|
||||
* determine which NDFC register to access.
|
||||
*
|
||||
* There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
|
||||
*/
|
||||
static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
hwctl |= 0x1;
|
||||
else
|
||||
hwctl &= ~0x1;
|
||||
if ( ctrl & NAND_ALE )
|
||||
hwctl |= 0x2;
|
||||
else
|
||||
hwctl &= ~0x2;
|
||||
if ( (ctrl & NAND_NCE) != NAND_NCE)
|
||||
writeb(0x00, &(alpr_ndfc->term));
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static u_char alpr_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
return readb(&(alpr_ndfc->data));
|
||||
}
|
||||
|
||||
static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand = mtd->priv;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (hwctl & 0x1)
|
||||
/*
|
||||
* IO_ADDR_W used as CMD[i] reg to support multiple NAND
|
||||
* chips.
|
||||
*/
|
||||
writeb(buf[i], nand->IO_ADDR_W);
|
||||
else if (hwctl & 0x2)
|
||||
writeb(buf[i], &(alpr_ndfc->addr_wait));
|
||||
else
|
||||
writeb(buf[i], &(alpr_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = readb(&(alpr_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static int alpr_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
/*
|
||||
* Blocking read to wait for NAND to be ready
|
||||
*/
|
||||
(void)readb(&(alpr_ndfc->addr_wait));
|
||||
|
||||
/*
|
||||
* Return always true
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
|
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Reference hardware control function */
|
||||
nand->cmd_ctrl = alpr_nand_hwcontrol;
|
||||
nand->read_byte = alpr_nand_read_byte;
|
||||
nand->write_buf = alpr_nand_write_buf;
|
||||
nand->read_buf = alpr_nand_read_buf;
|
||||
nand->dev_ready = alpr_nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -1,7 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_ALPR=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
@ -12,7 +12,8 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
cam_enc_4xx arm arm926ejs - - Heiko Schocher <hs@denx.de>
|
||||
alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
|
||||
atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
||||
atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
||||
atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
|
||||
|
||||
@ -1,351 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ALPR 1 /* Board is ebony */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
|
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
|
||||
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
|
||||
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
|
||||
|
||||
|
||||
#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
|
||||
#undef CONFIG_SDRAM_ECC /* enable ECC support */
|
||||
#define CONFIG_SYS_SDRAM_TABLE { \
|
||||
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
|
||||
{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (PCF8594C)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
|
||||
/* 8 byte page write mode using */
|
||||
/* last 3 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run kernelx\" to boot the system;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth3\0" \
|
||||
"hostname=alpr\0" \
|
||||
"fdt_file=alpr/alpr.dtb\0" \
|
||||
"fdt_addr=400000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath} ${init}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
|
||||
"mem=193M\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"net_nfs_fdt=tftp 200000 ${bootfile};" \
|
||||
"tftp ${fdt_addr} ${fdt_file};" \
|
||||
"run nfsargs addip addtty;" \
|
||||
"bootm 200000 - ${fdt_addr}\0" \
|
||||
"rootpath=/opt/projects/alpr/nfs_root\0" \
|
||||
"bootfile=/alpr/uImage\0" \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff10000\0" \
|
||||
"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load update\0" \
|
||||
"ethprime=ppc_4xx_eth3\0" \
|
||||
"ethact=ppc_4xx_eth3\0" \
|
||||
"autoload=no\0" \
|
||||
"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
|
||||
"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
|
||||
"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
|
||||
"rootfstype=jffs2 init=/sbin/init\0" \
|
||||
"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
|
||||
";bootm 200000\0" \
|
||||
"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
|
||||
"addtty;bootm 200000\0" \
|
||||
"kernel1=setenv actkernel 'kernel1';run load_fpga " \
|
||||
"kernel1_mtd\0" \
|
||||
"kernel2=setenv actkernel 'kernel2';run load_fpga " \
|
||||
"kernel2_mtd\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run kernel2"
|
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
|
||||
#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
|
||||
#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_FPGA_LOADMK
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
|
||||
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
|
||||
#define CONFIG_SYS_PCI_MASTER_INIT
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_ALTERA
|
||||
#define CONFIG_FPGA_CYCLON2
|
||||
#define CONFIG_SYS_FPGA_CHECK_CTRLC
|
||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
|
||||
Reihe geschaltet -> sollte gehen,
|
||||
aufpassen mit Datasize ist jetzt
|
||||
halt doppelt so gross ... Seite 306
|
||||
ist das mit den multiple Device in PS
|
||||
Mode erklaert ...*/
|
||||
|
||||
/* FPGA program pin configuration */
|
||||
#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
|
||||
#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
|
||||
#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
|
||||
#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
|
||||
#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
|
||||
|
||||
#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
|
||||
#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
|
||||
#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
|
||||
#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
|
||||
#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
|
||||
#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
|
||||
#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 4
|
||||
#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
|
||||
CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
|
||||
#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
|
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (NAND-FLASH) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
|
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user