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board: sama5d4ek: fix DD2 configuration

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Fix the DDR2 configuration to make SPL work.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
This commit is contained in:
Wenyou Yang 2017-03-23 14:35:33 +08:00 committed by Simon Glass
parent 62904b7346
commit 0d00f9b6c1
2 changed files with 21 additions and 2 deletions
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7
arch/arm/mach-at91/include/mach/atmel_mpddrc.h
View File

@ -186,9 +186,14 @@ int ddr3_init(const unsigned int base,
#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
#define ATMEL_MPDDRC_IO_CALIBR_TZQIO 0x7f
#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8)
#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8)
#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16)
#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16)
#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20)
#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20)
#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4)
/* Bit field in Read Data Path Register */

16
board/atmel/sama5d4ek/sama5d4ek.c
View File

@ -230,7 +230,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
ATMEL_MPDDRC_CR_NB_8BANKS |
ATMEL_MPDDRC_CR_NDQS_DISABLED |
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
@ -260,6 +259,8 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
u32 tmp;
ddr2_conf(&ddr2);
@ -267,6 +268,19 @@ void mem_init(void)
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_DDR);
tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
writel(tmp, &mpddr->rd_data_path);
tmp = readl(&mpddr->io_calibr);
tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
ATMEL_MPDDRC_IO_CALIBR_TZQIO |
ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
writel(tmp, &mpddr->io_calibr);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}