arm: mvebu: Add basic support for the Marvell Armada 375 SoC
This patch adds basic support for the Armada 375. Please note that currently the SerDes and DDR3 init code for the A375 is not included / enabled. This will be done in a later, follow-up patch. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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Stefan Roese
parent
0b45a79faa
commit
09e89ab4af
@ -15,6 +15,7 @@ else
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obj-y = cpu.o
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obj-y += dram.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
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obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
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obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
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endif
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@ -54,17 +54,57 @@ int mvebu_soc_family(void)
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case SOC_MV78260_ID:
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case SOC_MV78460_ID:
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return MVEBU_SOC_AXP;
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case SOC_88F6720_ID:
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return MVEBU_SOC_A375;
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case SOC_88F6810_ID:
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case SOC_88F6820_ID:
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case SOC_88F6828_ID:
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return MVEBU_SOC_A38X;
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}
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return MVEBU_SOC_UNKNOWN;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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#if defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_375)
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/* SAR frequency values for Armada 375 */
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static const struct sar_freq_modes sar_freq_tab[] = {
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{ 0, 0x0, 266, 133, 266 },
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{ 1, 0x0, 333, 167, 167 },
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{ 2, 0x0, 333, 167, 222 },
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{ 3, 0x0, 333, 167, 333 },
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{ 4, 0x0, 400, 200, 200 },
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{ 5, 0x0, 400, 200, 267 },
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{ 6, 0x0, 400, 200, 400 },
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{ 7, 0x0, 500, 250, 250 },
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{ 8, 0x0, 500, 250, 334 },
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{ 9, 0x0, 500, 250, 500 },
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{ 10, 0x0, 533, 267, 267 },
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{ 11, 0x0, 533, 267, 356 },
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{ 12, 0x0, 533, 267, 533 },
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{ 13, 0x0, 600, 300, 300 },
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{ 14, 0x0, 600, 300, 400 },
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{ 15, 0x0, 600, 300, 600 },
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{ 16, 0x0, 666, 333, 333 },
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{ 17, 0x0, 666, 333, 444 },
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{ 18, 0x0, 666, 333, 666 },
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{ 19, 0x0, 800, 400, 267 },
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{ 20, 0x0, 800, 400, 400 },
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{ 21, 0x0, 800, 400, 534 },
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{ 22, 0x0, 900, 450, 300 },
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{ 23, 0x0, 900, 450, 450 },
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{ 24, 0x0, 900, 450, 600 },
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{ 25, 0x0, 1000, 500, 500 },
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{ 26, 0x0, 1000, 500, 667 },
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{ 27, 0x0, 1000, 333, 500 },
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{ 28, 0x0, 400, 400, 400 },
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{ 29, 0x0, 1100, 550, 550 },
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{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
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};
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#elif defined(CONFIG_ARMADA_38X)
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/* SAR frequency values for Armada 38x */
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static const struct sar_freq_modes sar_freq_tab[] = {
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{ 0x0, 0x0, 666, 333, 333 },
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@ -98,9 +138,13 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
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u32 freq;
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int i;
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#if defined(CONFIG_ARMADA_375)
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val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
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#else
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val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
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#endif
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freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
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#if !defined(CONFIG_ARMADA_38X)
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#if defined(SAR2_CPU_FREQ_MASK)
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/*
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* Shift CPU0 clock frequency select bit from SAR2 register
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* into correct position
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@ -110,7 +154,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
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#endif
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for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
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if (sar_freq_tab[i].val == freq) {
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#if defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
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*sar_freq = sar_freq_tab[i];
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return;
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#else
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@ -152,6 +196,9 @@ int print_cpuinfo(void)
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case SOC_MV78460_ID:
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puts("MV78460-");
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break;
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case SOC_88F6720_ID:
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puts("MV88F6720-");
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break;
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case SOC_88F6810_ID:
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puts("MV88F6810-");
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break;
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@ -180,6 +227,17 @@ int print_cpuinfo(void)
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A375) {
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switch (revid) {
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case MV_88F67XX_A0_ID:
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puts("A0");
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break;
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default:
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printf("?? (%x)", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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switch (revid) {
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case MV_88F68XX_Z1_ID:
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@ -17,7 +17,8 @@
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#include <asm/arch/soc.h>
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#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
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|| defined(CONFIG_ARMADA_38X)
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/*
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* Set this for the common xor register definitions needed in dram.c
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* for A38x as well here.
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@ -78,8 +79,10 @@
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_MII /* expose smi ove miiphy interface */
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#if !defined(CONFIG_ARMADA_375)
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#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
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#define CONFIG_PHYLIB
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#endif
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
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#define CONFIG_ARP_TIMEOUT 200
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@ -61,6 +61,7 @@ enum cpu_attrib {
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enum {
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MVEBU_SOC_AXP,
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MVEBU_SOC_A375,
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MVEBU_SOC_A38X,
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MVEBU_SOC_UNKNOWN,
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};
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@ -89,7 +90,11 @@ struct mbus_win {
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* Ref: Datasheet sec:A.28
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*/
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struct mvebu_system_registers {
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#if defined(CONFIG_ARMADA_375)
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u8 pad1[0x54];
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#else
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u8 pad1[0x60];
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#endif
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u32 rstoutn_mask; /* 0x60 */
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u32 sys_soft_rst; /* 0x64 */
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};
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@ -14,10 +14,14 @@
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#define SOC_MV78230_ID 0x7823
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#define SOC_MV78260_ID 0x7826
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#define SOC_MV78460_ID 0x7846
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#define SOC_88F6720_ID 0x6720
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#define SOC_88F6810_ID 0x6810
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#define SOC_88F6820_ID 0x6820
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#define SOC_88F6828_ID 0x6828
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/* A375 revisions */
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#define MV_88F67XX_A0_ID 0x3
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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@ -106,7 +110,20 @@
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#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
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#define BOOTROM_ERR_MODE_UART 0x6
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#if defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_375)
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/* SAR values for Armada 375 */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
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#define SAR_CPU_FREQ_OFFS 17
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define BOOT_DEV_SEL_OFFS 3
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#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_UART 0x30
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#define BOOT_FROM_SPI 0x38
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#elif defined(CONFIG_ARMADA_38X)
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/* SAR values for Armada 38x */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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@ -99,11 +99,14 @@ void board_init_f(ulong dummy)
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timer_init();
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/* Armada 375 does not support SerDes and DDR3 init yet */
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#if !defined(CONFIG_ARMADA_375)
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/* First init the serdes PHY's */
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serdes_phy_config();
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/* Setup DDR */
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ddr3_init();
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#endif
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/*
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* Return to the BootROM to continue the Marvell xmodem
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