ARM: sunxi: Add sun6i specific PSCI implementation
This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Chen-Yu Tsai
Hans de Goede
parent
d4611aff4d
commit
073f298438
@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
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ifndef CONFIG_SPL_BUILD
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ifdef CONFIG_ARMV7_PSCI
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obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o
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obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o
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endif
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endif
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276
arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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276
arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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@ -0,0 +1,276 @@
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/*
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* Copyright (C) 2015 - Chen-Yu Tsai
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* Author: Chen-Yu Tsai <wens@csie.org>
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*
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* Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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#include <asm/psci.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory layout:
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*
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* SECURE_RAM to text_end :
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* ._secure_text section
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* text_end to ALIGN_PAGE(text_end):
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* nothing
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
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* 1kB of stack per CPU (4 CPUs max).
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*/
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
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#define TEN_MS (10 * ONE_MS)
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#define GICD_BASE 0x1c81000
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#define GICC_BASE 0x1c82000
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.macro timer_wait reg, ticks
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@ Program CNTP_TVAL
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movw \reg, #(\ticks & 0xffff)
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movt \reg, #(\ticks >> 16)
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mcr p15, 0, \reg, c14, c2, 0
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isb
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@ Enable physical timer, mask interrupt
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mov \reg, #3
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mcr p15, 0, \reg, c14, c2, 1
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@ Poll physical timer until ISTATUS is on
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1: isb
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mrc p15, 0, \reg, c14, c2, 1
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ands \reg, \reg, #4
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bne 1b
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@ Disable timer
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mov \reg, #0
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mcr p15, 0, \reg, c14, c2, 1
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isb
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.endm
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.globl psci_fiq_enter
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psci_fiq_enter:
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push {r0-r12}
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@ Switch to secure
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mrc p15, 0, r7, c1, c1, 0
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bic r8, r7, #1
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mcr p15, 0, r8, c1, c1, 0
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isb
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@ Validate reason based on IAR and acknowledge
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movw r8, #(GICC_BASE & 0xffff)
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movt r8, #(GICC_BASE >> 16)
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ldr r9, [r8, #GICC_IAR]
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movw r10, #0x3ff
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movt r10, #0
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cmp r9, r10 @ skip spurious interrupt 1023
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beq out
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movw r10, #0x3fe @ ...and 1022
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cmp r9, r10
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beq out
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str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
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dsb
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@ Compute CPU number
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lsr r9, r9, #10
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and r9, r9, #0xf
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN6I_CPUCFG_BASE >> 16)
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@ Wait for the core to enter WFI
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lsl r11, r9, #6 @ x64
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add r11, r11, r8
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1: ldr r10, [r11, #0x48]
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tst r10, #(1 << 2)
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bne 2f
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timer_wait r10, ONE_MS
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b 1b
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@ Reset CPU
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2: mov r10, #0
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str r10, [r11, #0x40]
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@ Lock CPU
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mov r10, #1
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lsl r11, r10, r9 @ r11 is now CPU mask
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ldr r10, [r8, #0x1e4]
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bic r10, r10, r11
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str r10, [r8, #0x1e4]
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movw r8, #(SUNXI_PRCM_BASE & 0xffff)
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movt r8, #(SUNXI_PRCM_BASE >> 16)
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@ Set power gating
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ldr r10, [r8, #0x100]
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orr r10, r10, r11
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str r10, [r8, #0x100]
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timer_wait r10, ONE_MS
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@ Activate power clamp
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lsl r12, r9, #2 @ x4
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add r12, r12, r8
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mov r10, #0xff
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str r10, [r12, #0x140]
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN6I_CPUCFG_BASE >> 16)
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@ Unlock CPU
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ldr r10, [r8, #0x1e4]
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orr r10, r10, r11
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str r10, [r8, #0x1e4]
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@ Restore security level
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out: mcr p15, 0, r7, c1, c1, 0
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pop {r0-r12}
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subs pc, lr, #4
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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push {lr}
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mov r0, r1
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bl psci_get_cpu_stack_top @ get stack top of target CPU
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str r2, [r0] @ store target PC at stack top
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dsb
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r0, #(SUN6I_CPUCFG_BASE >> 16)
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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mov r4, #1
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lsl r4, r4, r1
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ldr r6, =psci_cpu_entry
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str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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@ Assert reset on target CPU
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mov r6, #0
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5] @ Reset CPU
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@ l1 invalidate
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ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
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bic r6, r6, r4
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str r6, [r0, #0x184]
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@ Lock CPU (Disable external debug access)
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ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
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bic r6, r6, r4
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str r6, [r0, #0x1e4]
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movw r0, #(SUNXI_PRCM_BASE & 0xffff)
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movt r0, #(SUNXI_PRCM_BASE >> 16)
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@ Release power clamp
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lsl r5, r1, #2 @ 1 register per CPU
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add r5, r5, r0 @ PRCM
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movw r6, #0x1ff
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movt r6, #0
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1: lsrs r6, r6, #1
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str r6, [r5, #0x140] @ CPUx_PWR_CLAMP
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bne 1b
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timer_wait r6, TEN_MS
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@ Clear power gating
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ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING
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bic r6, r6, r4
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str r6, [r0, #0x100]
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@ re-calculate CPU control register address
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r0, #(SUN6I_CPUCFG_BASE >> 16)
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@ Deassert reset on target CPU
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mov r6, #3
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5]
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@ Unlock CPU (Enable external debug access)
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ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
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orr r6, r6, r4
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str r6, [r0, #0x1e4]
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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pop {pc}
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.globl psci_cpu_off
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psci_cpu_off:
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bl psci_cpu_off_common
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@ Ask CPU0 to pull the rug...
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movw r0, #(GICD_BASE & 0xffff)
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movt r0, #(GICD_BASE >> 16)
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movw r1, #15 @ SGI15
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movt r1, #1 @ Target is CPU0
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str r1, [r0, #GICD_SGIR]
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dsb
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1: wfi
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b 1b
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.globl psci_arch_init
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psci_arch_init:
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mov r6, lr
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movw r4, #(GICD_BASE & 0xffff)
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movt r4, #(GICD_BASE >> 16)
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ldr r5, [r4, #GICD_IGROUPRn]
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bic r5, r5, #(1 << 15) @ SGI15 as Group-0
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str r5, [r4, #GICD_IGROUPRn]
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mov r5, #0 @ Set SGI15 priority to 0
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strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
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add r4, r4, #0x1000 @ GICC address
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mov r5, #0xff
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str r5, [r4, #GICC_PMR] @ Be cool with non-secure
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ldr r5, [r4, #GICC_CTLR]
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orr r5, r5, #(1 << 3) @ Switch FIQEn on
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str r5, [r4, #GICC_CTLR]
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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orr r5, r5, #4 @ Enable FIQ in monitor mode
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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bl psci_get_cpu_id @ CPU ID => r0
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bl psci_get_cpu_stack_top @ stack top => r0
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mov sp, r0
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bx r6
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.globl psci_text_end
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psci_text_end:
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.popsection
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