74xx_7xx: CPCI750: Add ECC support on esd CPCI-CPU/750 board
Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. This patch also adds the "pldver" command to display the CPLD revision. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Reinhard Arlt
Wolfgang Denk
parent
1f9f3cf6cc
commit
0738e24e2c
@ -1090,3 +1090,15 @@ U_BOOT_CMD(
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"Show Marvell strapping register",
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"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
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);
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int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
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return 0;
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}
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U_BOOT_CMD(
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pldver, 1, 1, do_pldver,
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"Show PLD version",
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"Show PLD version)");
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@ -538,14 +538,14 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
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break;
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/*------------------------------------------------------------------------------------------------------------------------------*/
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#ifdef CONFIG_ECC
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#ifdef CONFIG_MV64360_ECC
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case 11: /* Error Check Type */
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dimmInfo->errorCheckType = data[i];
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DP (printf
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("Error Check Type (0=NONE): %d\n",
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dimmInfo->errorCheckType));
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break;
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#endif
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#endif /* of ifdef CONFIG_MV64360_ECC */
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/*------------------------------------------------------------------------------------------------------------------------------*/
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case 12: /* Refresh Interval */
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@ -1254,6 +1254,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
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ulong tmp;
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ulong tmp_sdram_mode = 0; /* 0x141c */
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ulong tmp_dunit_control_low = 0; /* 0x1404 */
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uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
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int i;
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/* sanity checking */
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@ -1269,7 +1270,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
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DP (printf
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("Module is registered, but we do not support registered Modules !!!\n"));
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/* delay line */
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set_dfcdlInit (); /* may be its not needed */
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DP (printf ("Delay line set done\n"));
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@ -1281,8 +1281,16 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
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("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
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}
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#ifdef CONFIG_MV64360_ECC
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if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
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/* DRAM has ECC, so turn it on */
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sdram_config_reg |= BIT18;
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DP(printf("Enabling ECC\n"));
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}
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#endif /* of ifdef CONFIG_MV64360_ECC */
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/* SDRAM configuration */
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GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
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GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
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DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
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/* SDRAM open pages controll keep open as much as I can */
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@ -1598,7 +1606,84 @@ dram_size(long int *base, long int maxsize)
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return maxsize;
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_MV64360_ECC
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/*
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* mv_dma_is_channel_active:
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* Checks if a engine is busy.
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*/
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int mv_dma_is_channel_active(int engine)
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{
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ulong data;
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data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
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if (data & BIT14) /* activity status */
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return 1;
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return 0;
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}
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/*
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* mv_dma_set_memory_space:
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* Set a DMA memory window for the DMA's address decoding map.
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*/
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int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
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ulong mem_space_attr, ulong base_address,
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ulong size)
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{
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ulong temp;
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/* The base address must be aligned to the size. */
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if (base_address % size != 0)
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return 0;
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if (size >= 0x10000) {
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size &= 0xffff0000;
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base_address = (base_address & 0xffff0000);
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/* Set the new attributes */
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GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
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(base_address | mem_space_target |
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mem_space_attr));
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GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
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(size - 1) & 0xffff0000);
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temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
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GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
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(temp & ~(BIT0 << mem_space)));
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return 1;
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}
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return 0;
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}
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/*
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* mv_dma_transfer:
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* Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
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*/
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int mv_dma_transfer(int engine, ulong source_addr,
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ulong dest_addr, ulong bytes, ulong command)
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{
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ulong eng_off_reg; /* Engine Offset Register */
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if (bytes > 0xffff)
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command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
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command = command | ((command >> 6) & 0x7);
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eng_off_reg = engine * 4;
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GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
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bytes);
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GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
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source_addr);
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GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
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dest_addr);
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command |= BIT12 /* DMA_CHANNEL_ENABLE */
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| BIT9; /* DMA_NON_CHAIN_MODE */
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/* Activate DMA engine By writting to mv_dma_control_register */
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GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
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return 1;
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}
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#endif /* of ifdef CONFIG_MV64360_ECC */
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/* ppcboot interface function to SDRAM init - this is where all the
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* controlling logic happens */
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@ -1607,10 +1692,13 @@ initdram(int board_type)
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{
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int s0 = 0, s1 = 0;
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int checkbank[4] = { [0 ... 3] = 0 };
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ulong bank_no, realsize, total, check;
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ulong realsize, total, check;
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AUX_MEM_DIMM_INFO dimmInfo1;
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AUX_MEM_DIMM_INFO dimmInfo2;
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int nhr;
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int bank_no, nhr;
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#ifdef CONFIG_MV64360_ECC
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ulong dest, mem_space_attr;
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#endif /* of ifdef CONFIG_MV64360_ECC */
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/* first, use the SPD to get info about the SDRAM/ DDRRAM */
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@ -1668,6 +1756,28 @@ initdram(int board_type)
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realsize = dram_size((long int *)total, check);
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memory_map_bank(bank_no, total, realsize);
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#ifdef CONFIG_MV64360_ECC
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if (((dimmInfo1.errorCheckType != 0) &&
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((dimmInfo2.errorCheckType != 0) ||
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(dimmInfo2.numOfModuleBanks == 0))) &&
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(CPCI750_ECC_TEST)) {
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printf("ECC Initialization of Bank %d:", bank_no);
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mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
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mv_dma_set_memory_space(0, 0, mem_space_attr, total,
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realsize);
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for (dest = total; dest < total + realsize;
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dest += _8M) {
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mv_dma_transfer(0, total, dest, _8M,
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BIT8 | /* DMA_DTL_128BYTES */
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BIT3 | /* DMA_HOLD_SOURCE_ADDR */
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BIT11); /* DMA_BLOCK_TRANSFER_MODE */
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while (mv_dma_is_channel_active(0))
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;
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}
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printf(" PASS\n");
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}
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#endif /* of ifdef CONFIG_MV64360_ECC */
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total += realsize;
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}
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@ -1700,3 +1810,30 @@ int set_dfcdlInit (void)
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return (0);
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}
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int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned int ecc_counter;
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unsigned int ecc_addr;
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GT_REG_READ(0x1458, &ecc_counter);
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GT_REG_READ(0x1450, &ecc_addr);
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GT_REG_WRITE(0x1450, 0);
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printf("Error Counter since Reset: %8d\n", ecc_counter);
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printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8);
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if (ecc_addr & 0x01)
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printf("double");
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else
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printf("single");
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printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
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return 0;
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}
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U_BOOT_CMD(
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show_ecc, 1, 1, do_show_ecc,
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"Show Marvell MV64360 ECC Info",
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"Show Marvell MV64360 ECC Counter and last error."
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);
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@ -59,7 +59,7 @@
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
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#undef CONFIG_ECC /* enable ECC support */
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#define CONFIG_MV64360_ECC /* enable ECC support */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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@ -628,5 +628,7 @@
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#define CONFIG_SYS_BOARD_ASM_INIT 1
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#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
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#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
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#define CONFIG_SYS_PLD_VER 0xf0e00000
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#endif /* __CONFIG_H */
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