rockchip: rk322x: add clock driver
Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang
Philipp Tomsich
parent
236776d63f
commit
045029cbd1
215
arch/arm/include/asm/arch-rockchip/cru_rk322x.h
Normal file
215
arch/arm/include/asm/arch-rockchip/cru_rk322x.h
Normal file
@ -0,0 +1,215 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK322X_H
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#define _ASM_ARCH_CRU_RK322X_H
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (594 * MHz)
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#define CORE_PERI_HZ 150000000
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#define CORE_ACLK_HZ 300000000
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#define BUS_ACLK_HZ 148500000
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#define BUS_HCLK_HZ 148500000
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#define BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk322x_clk_priv {
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struct rk322x_cru *cru;
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ulong rate;
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};
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struct rk322x_cru {
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struct rk322x_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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} pll[4];
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unsigned int reserved0[4];
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unsigned int cru_mode_con;
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unsigned int cru_clksel_con[35];
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unsigned int cru_clkgate_con[16];
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unsigned int cru_softrst_con[9];
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unsigned int cru_misc_con;
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unsigned int reserved1[2];
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unsigned int cru_glb_cnt_th;
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unsigned int reserved2[3];
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unsigned int cru_glb_rst_st;
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unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
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unsigned int cru_sdmmc_con[2];
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unsigned int cru_sdio_con[2];
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unsigned int reserved4[2];
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unsigned int cru_emmc_con[2];
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unsigned int reserved5[4];
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unsigned int cru_glb_srst_fst_value;
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unsigned int cru_glb_srst_snd_value;
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unsigned int cru_pll_mask_con;
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};
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check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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};
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_RST_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* CRU_MODE */
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GPLL_MODE_SHIFT = 12,
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GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
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GPLL_MODE_SLOW = 0,
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GPLL_MODE_NORM,
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CPLL_MODE_SHIFT = 8,
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CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
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CPLL_MODE_SLOW = 0,
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CPLL_MODE_NORM,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW = 0,
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DPLL_MODE_NORM,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
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APLL_MODE_SLOW = 0,
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APLL_MODE_NORM,
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/* CRU_CLK_SEL0_CON */
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BUS_ACLK_PLL_SEL_SHIFT = 13,
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BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
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BUS_ACLK_PLL_SEL_APLL = 0,
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BUS_ACLK_PLL_SEL_GPLL,
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BUS_ACLK_PLL_SEL_HDMIPLL,
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BUS_ACLK_DIV_SHIFT = 8,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 6,
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CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_CLK_PLL_SEL_DPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL1_CON */
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BUS_PCLK_DIV_SHIFT = 12,
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BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 8,
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BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
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CORE_PERI_DIV_SHIFT = 0,
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CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
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/* CRU_CLKSEL5_CON */
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GMAC_OUT_PLL_SHIFT = 15,
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GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
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GMAC_OUT_DIV_SHIFT = 8,
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GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
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MAC_PLL_SEL_SHIFT = 7,
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MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
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RMII_EXTCLK_SLE_SHIFT = 5,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
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RMII_EXTCLK_SEL_INT = 0,
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RMII_EXTCLK_SEL_EXT,
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CLK_MAC_DIV_SHIFT = 0,
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CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
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/* CRU_CLKSEL10_CON */
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PERI_PCLK_DIV_SHIFT = 12,
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PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
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PERI_PLL_SEL_SHIFT = 10,
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PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_CPLL = 0,
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PERI_PLL_GPLL,
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PERI_PLL_HDMIPLL,
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLKSEL11_CON */
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EMMC_PLL_SHIFT = 12,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_APLL = 0,
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EMMC_SEL_DPLL,
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EMMC_SEL_GPLL,
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EMMC_SEL_24M,
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SDIO_PLL_SHIFT = 10,
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SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
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SDIO_SEL_APLL = 0,
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SDIO_SEL_DPLL,
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SDIO_SEL_GPLL,
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SDIO_SEL_24M,
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MMC0_PLL_SHIFT = 8,
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MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
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MMC0_SEL_APLL = 0,
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MMC0_SEL_DPLL,
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MMC0_SEL_GPLL,
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MMC0_SEL_24M,
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
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/* CRU_CLKSEL12_CON */
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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SDIO_DIV_SHIFT = 0,
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SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
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/* CRU_CLKSEL26_CON */
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DDR_CLK_PLL_SEL_SHIFT = 8,
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DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
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DDR_CLK_SEL_DPLL = 0,
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DDR_CLK_SEL_GPLL,
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DDR_CLK_SEL_APLL,
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DDR_DIV_SEL_SHIFT = 0,
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DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
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/* CRU_CLKSEL27_CON */
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VOP_DCLK_DIV_SHIFT = 8,
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VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
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VOP_PLL_SEL_SHIFT = 1,
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VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
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/* CRU_CLKSEL29_CON */
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GMAC_CLK_SRC_SHIFT = 12,
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GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
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/* CRU_SOFTRST5_CON */
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DDRCTRL_PSRST_SHIFT = 11,
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DDRCTRL_SRST_SHIFT = 10,
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DDRPHY_PSRST_SHIFT = 9,
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DDRPHY_SRST_SHIFT = 8,
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};
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#endif
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@ -6,6 +6,7 @@
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obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
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obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
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obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
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obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
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obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
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obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
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413
drivers/clk/rockchip/clk_rk322x.c
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413
drivers/clk/rockchip/clk_rk322x.c
Normal file
@ -0,0 +1,413 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk322x.h>
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#include <asm/arch/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3228-cru.h>
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#include <linux/log2.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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VCO_MAX_HZ = 3200U * 1000000,
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VCO_MIN_HZ = 800 * 1000000,
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OUTPUT_MAX_HZ = 3200U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk322x_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static void rkclk_init(struct rk322x_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select apll as pd_bus bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
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hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
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aclk_div << BUS_ACLK_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
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pclk_div << BUS_PCLK_DIV_SHIFT |
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hclk_div << BUS_HCLK_DIV_SHIFT);
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/*
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* select gpll as pd_peri bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
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PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
|
||||
pclk_div << PERI_PCLK_DIV_SHIFT |
|
||||
hclk_div << PERI_HCLK_DIV_SHIFT |
|
||||
aclk_div << PERI_ACLK_DIV_SHIFT);
|
||||
|
||||
/* PLL enter normal-mode */
|
||||
rk_clrsetreg(&cru->cru_mode_con,
|
||||
GPLL_MODE_MASK | APLL_MODE_MASK,
|
||||
GPLL_MODE_NORM << GPLL_MODE_SHIFT |
|
||||
APLL_MODE_NORM << APLL_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/* Get pll rate by id */
|
||||
static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
|
||||
enum rk_clk_id clk_id)
|
||||
{
|
||||
uint32_t refdiv, fbdiv, postdiv1, postdiv2;
|
||||
uint32_t con;
|
||||
int pll_id = rk_pll_id(clk_id);
|
||||
struct rk322x_pll *pll = &cru->pll[pll_id];
|
||||
static u8 clk_shift[CLK_COUNT] = {
|
||||
0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
|
||||
GPLL_MODE_SHIFT, 0xff
|
||||
};
|
||||
static u32 clk_mask[CLK_COUNT] = {
|
||||
0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
|
||||
GPLL_MODE_MASK, 0xff
|
||||
};
|
||||
uint shift;
|
||||
uint mask;
|
||||
|
||||
con = readl(&cru->cru_mode_con);
|
||||
shift = clk_shift[clk_id];
|
||||
mask = clk_mask[clk_id];
|
||||
|
||||
switch ((con & mask) >> shift) {
|
||||
case GPLL_MODE_SLOW:
|
||||
return OSC_HZ;
|
||||
case GPLL_MODE_NORM:
|
||||
|
||||
/* normal mode */
|
||||
con = readl(&pll->con0);
|
||||
postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
|
||||
fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
|
||||
con = readl(&pll->con1);
|
||||
postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
|
||||
refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
|
||||
return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
|
||||
default:
|
||||
return 32768;
|
||||
}
|
||||
}
|
||||
|
||||
static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
|
||||
int periph)
|
||||
{
|
||||
uint src_rate;
|
||||
uint div, mux;
|
||||
u32 con;
|
||||
|
||||
switch (periph) {
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
con = readl(&cru->cru_clksel_con[11]);
|
||||
mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
|
||||
con = readl(&cru->cru_clksel_con[12]);
|
||||
div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
|
||||
break;
|
||||
case HCLK_SDMMC:
|
||||
case SCLK_SDMMC:
|
||||
con = readl(&cru->cru_clksel_con[11]);
|
||||
mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
|
||||
div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
|
||||
return DIV_TO_RATE(src_rate, div);
|
||||
}
|
||||
|
||||
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
|
||||
int periph, uint freq)
|
||||
{
|
||||
int src_clk_div;
|
||||
int mux;
|
||||
|
||||
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
|
||||
|
||||
/* mmc clock auto divide 2 in internal */
|
||||
src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
|
||||
|
||||
if (src_clk_div > 0x7f) {
|
||||
src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
|
||||
mux = EMMC_SEL_24M;
|
||||
} else {
|
||||
mux = EMMC_SEL_GPLL;
|
||||
}
|
||||
|
||||
switch (periph) {
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
rk_clrsetreg(&cru->cru_clksel_con[11],
|
||||
EMMC_PLL_MASK,
|
||||
mux << EMMC_PLL_SHIFT);
|
||||
rk_clrsetreg(&cru->cru_clksel_con[12],
|
||||
EMMC_DIV_MASK,
|
||||
(src_clk_div - 1) << EMMC_DIV_SHIFT);
|
||||
break;
|
||||
case HCLK_SDMMC:
|
||||
case SCLK_SDMMC:
|
||||
rk_clrsetreg(&cru->cru_clksel_con[11],
|
||||
MMC0_PLL_MASK | MMC0_DIV_MASK,
|
||||
mux << MMC0_PLL_SHIFT |
|
||||
(src_clk_div - 1) << MMC0_DIV_SHIFT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
|
||||
}
|
||||
|
||||
static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
|
||||
{
|
||||
struct pll_div dpll_cfg;
|
||||
|
||||
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
|
||||
switch (set_rate) {
|
||||
case 400*MHz:
|
||||
dpll_cfg = (struct pll_div)
|
||||
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
|
||||
break;
|
||||
case 600*MHz:
|
||||
dpll_cfg = (struct pll_div)
|
||||
{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
|
||||
break;
|
||||
case 800*MHz:
|
||||
dpll_cfg = (struct pll_div)
|
||||
{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
|
||||
break;
|
||||
}
|
||||
|
||||
/* pll enter slow-mode */
|
||||
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
|
||||
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
|
||||
rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
|
||||
/* PLL enter normal-mode */
|
||||
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
|
||||
DPLL_MODE_NORM << DPLL_MODE_SHIFT);
|
||||
|
||||
return set_rate;
|
||||
}
|
||||
static ulong rk322x_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
ulong rate, gclk_rate;
|
||||
|
||||
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
||||
switch (clk->id) {
|
||||
case 0 ... 63:
|
||||
rate = rkclk_pll_get_rate(priv->cru, clk->id);
|
||||
break;
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
case HCLK_SDMMC:
|
||||
case SCLK_SDMMC:
|
||||
rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
ulong new_rate, gclk_rate;
|
||||
|
||||
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
||||
switch (clk->id) {
|
||||
case HCLK_EMMC:
|
||||
case SCLK_EMMC:
|
||||
case HCLK_SDMMC:
|
||||
case SCLK_SDMMC:
|
||||
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
|
||||
clk->id, rate);
|
||||
break;
|
||||
case CLK_DDR:
|
||||
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return new_rate;
|
||||
}
|
||||
|
||||
static struct clk_ops rk322x_clk_ops = {
|
||||
.get_rate = rk322x_clk_get_rate,
|
||||
.set_rate = rk322x_clk_set_rate,
|
||||
};
|
||||
|
||||
static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct rk322x_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk322x_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct rk322x_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
rkclk_init(priv->cru);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk322x_clk_bind(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* The reset driver does not have a device node, so bind it here */
|
||||
ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
|
||||
if (ret)
|
||||
debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id rk322x_clk_ids[] = {
|
||||
{ .compatible = "rockchip,rk3228-cru" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk322x_cru) = {
|
||||
.name = "clk_rk322x",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = rk322x_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
|
||||
.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
|
||||
.ops = &rk322x_clk_ops,
|
||||
.bind = rk322x_clk_bind,
|
||||
.probe = rk322x_clk_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user