ARM: rmobile: Add Beacon EmbeddedWorks RZG2H Dev Kit
The Beacon EmbeddedWorks kit is based on the R8A774E1 SoC also known as the RZ/G2H. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. It shares much of the same design as the RZ/G2M and RZ/G2N dev kits. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Marek Vasut
parent
6001b49920
commit
0099dfd5e5
@ -810,6 +810,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
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dtb-$(CONFIG_RCAR_GEN3) += \
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r8a774a1-beacon-rzg2m-kit.dtb \
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r8a774b1-beacon-rzg2n-kit.dtb \
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r8a774e1-beacon-rzg2h-kit.dtb \
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r8a77950-ulcb-u-boot.dtb \
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r8a77950-salvator-x-u-boot.dtb \
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r8a77960-ulcb-u-boot.dtb \
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44
arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
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44
arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020 Compass Electronics Group, LLC
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*/
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/ {
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&cpg {
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u-boot,dm-pre-reloc;
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};
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&extal_clk {
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u-boot,dm-pre-reloc;
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};
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&prr {
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u-boot,dm-pre-reloc;
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};
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&extalr_clk {
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u-boot,dm-pre-reloc;
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};
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&sdhi0 {
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/delete-property/ cd-gpios;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr104;
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max-frequency = <208000000>;
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};
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&sdhi2 {
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status = "disabled";
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};
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&sdhi3 {
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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};
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71
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
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71
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
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@ -0,0 +1,71 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020, Compass Electronics Group, LLC
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*/
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/dts-v1/;
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#include "r8a774e1.dtsi"
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#include "beacon-renesom-som.dtsi"
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#include "beacon-renesom-baseboard.dtsi"
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/ {
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model = "Beacon Embedded Works RZ/G2H Development Kit";
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compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
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aliases {
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serial0 = &scif2;
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serial1 = &hscif0;
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serial2 = &hscif1;
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serial3 = &scif0;
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serial4 = &hscif2;
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serial5 = &scif5;
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serial6 = &scif4;
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ethernet0 = &avb;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@500000000 {
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device_type = "memory";
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reg = <0x5 0x00000000 0x0 0x80000000>;
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};
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 721>,
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<&versaclock5 1>,
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<&x302_clk>,
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<&versaclock5 2>;
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clock-names = "du.0", "du.1", "du.3",
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"dclkin.0", "dclkin.1", "dclkin.3";
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};
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/* Reference versaclock instead of audio_clk_a */
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&rcar_sound {
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clocks = <&cpg CPG_MOD 1005>,
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<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
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<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
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<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
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<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
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<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
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<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
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<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
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<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
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<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
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<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
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<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
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<&versaclock6_bb 4>, <&audio_clk_b>,
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<&audio_clk_c>,
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<&cpg CPG_CORE R8A774E1_CLK_S0D4>;
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};
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@ -60,6 +60,11 @@ choice
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prompt "Renesas ARM64 SoCs board select"
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optional
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config TARGET_BEACON_RZG2H
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bool "Beacon EmbeddedWorks RZ/G2H Dev Kit"
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select R8A774E1
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select PINCTRL_PFC_R8A774E1
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config TARGET_BEACON_RZG2M
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bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
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select R8A774A1
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@ -1,4 +1,4 @@
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if TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
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if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
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config SYS_SOC
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default "rmobile"
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@ -5,3 +5,4 @@ F: board/beacon/beacon-rzg2m/
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F: include/configs/beacon-rzg2m.h
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F: configs/r8a774a1_beacon_defconfig
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F: configs/r8a774b1_beacon_defconfig
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F: configs/r8a774e1_beacon_defconfig
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67
configs/r8a774e1_beacon_defconfig
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67
configs/r8a774e1_beacon_defconfig
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@ -0,0 +1,67 @@
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CONFIG_ARM=y
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0x50000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ENV_OFFSET=0x0
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CONFIG_DM_GPIO=y
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CONFIG_RCAR_GEN3=y
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CONFIG_R8A774E1=y
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CONFIG_TARGET_BEACON_RZG2H=y
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# CONFIG_SPL is not set
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CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
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CONFIG_FIT=y
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CONFIG_SUPPORT_RAW_INITRD=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_DEFAULT_FDT_FILE="r8a774e1-beacon-rzg2h-kit.dtb"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PART=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_SYS_MMC_ENV_PART=2
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CONFIG_VERSION_VARIABLE=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CLK=y
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CONFIG_CLK_RENESAS=y
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CONFIG_RCAR_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_RCAR_I2C=y
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CONFIG_SYS_I2C_RCAR_IIC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_RENESAS_SDHI=y
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CONFIG_BITBANGMII=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_RENESAS_RAVB=y
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CONFIG_PINCTRL_PFC_R8A774E1=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_STORAGE=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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