u-boot/arch/arm/mach-rockchip/rk3036/Makefile

#
# (C) Copyright 2015 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier:     GPL-2.0+
#

ifndef CONFIG_SPL_BUILD
obj-y += reset_rk3036.o
obj-y += syscon_rk3036.o
endif

obj-y += sdram_rk3036.o
obj-y += save_boot_param.o
rockchip: rk3036: Add Soc reset driver We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:18 +00:00			`#`
			`# (C) Copyright 2015 Rockchip Electronics Co., Ltd`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`ifndef CONFIG_SPL_BUILD`
			`obj-y += reset_rk3036.o`
rockchip: rk3036: Add a simple syscon driver Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:19 +00:00			`obj-y += syscon_rk3036.o`
rockchip: rk3036: Add Soc reset driver We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:18 +00:00			`endif`
rockchip: add rk3036 sdram driver add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:26 +00:00
			`obj-y += sdram_rk3036.o`
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288 2015-11-17 06:20:27 +00:00			`obj-y += save_boot_param.o`