forked from Minki/linux
a862391871
Enable using VG1 and VG2 for planes. Currently YUV/CSC or scaling is not enabled, but ARGB and xRGB blending is. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
241 lines
7.1 KiB
C
241 lines
7.1 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MDP4_KMS_H__
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#define __MDP4_KMS_H__
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "msm_drv.h"
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#include "mdp4.xml.h"
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/* For transiently registering for different MDP4 irqs that various parts
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* of the KMS code need during setup/configuration. We these are not
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* necessarily the same as what drm_vblank_get/put() are requesting, and
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* the hysteresis in drm_vblank_put() is not necessarily desirable for
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* internal housekeeping related irq usage.
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*/
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struct mdp4_irq {
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struct list_head node;
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uint32_t irqmask;
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bool registered;
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void (*irq)(struct mdp4_irq *irq, uint32_t irqstatus);
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};
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struct mdp4_kms {
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struct msm_kms base;
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struct drm_device *dev;
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int rev;
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/* mapper-id used to request GEM buffer mapped for scanout: */
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int id;
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void __iomem *mmio;
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struct regulator *dsi_pll_vdda;
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struct regulator *dsi_pll_vddio;
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struct regulator *vdd;
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struct clk *clk;
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struct clk *pclk;
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struct clk *lut_clk;
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/* irq handling: */
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bool in_irq;
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struct list_head irq_list; /* list of mdp4_irq */
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uint32_t vblank_mask; /* irq bits set for userspace vblank */
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struct mdp4_irq error_handler;
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};
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#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
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/* platform config data (ie. from DT, or pdata) */
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struct mdp4_platform_config {
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struct iommu_domain *iommu;
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uint32_t max_clk;
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};
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struct mdp4_format {
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struct msm_format base;
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enum mdp4_bpc bpc_r, bpc_g, bpc_b;
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enum mdp4_bpc_alpha bpc_a;
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uint8_t unpack[4];
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bool alpha_enable, unpack_tight;
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uint8_t cpp, unpack_count;
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};
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#define to_mdp4_format(x) container_of(x, struct mdp4_format, base)
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static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
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{
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msm_writel(data, mdp4_kms->mmio + reg);
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}
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static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
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{
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return msm_readl(mdp4_kms->mmio + reg);
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}
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static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
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{
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switch (pipe) {
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case VG1: return MDP4_OVERLAY_FLUSH_VG1;
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case VG2: return MDP4_OVERLAY_FLUSH_VG2;
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case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
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case RGB2: return MDP4_OVERLAY_FLUSH_RGB1;
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default: return 0;
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}
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}
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static inline uint32_t ovlp2flush(int ovlp)
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{
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switch (ovlp) {
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case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
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case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
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default: return 0;
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}
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}
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static inline uint32_t dma2irq(enum mdp4_dma dma)
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{
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switch (dma) {
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case DMA_P: return MDP4_IRQ_DMA_P_DONE;
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case DMA_S: return MDP4_IRQ_DMA_S_DONE;
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case DMA_E: return MDP4_IRQ_DMA_E_DONE;
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default: return 0;
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}
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}
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static inline uint32_t dma2err(enum mdp4_dma dma)
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{
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switch (dma) {
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case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
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case DMA_S: return 0; // ???
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case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
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default: return 0;
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}
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}
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static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
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enum mdp4_mixer_stage_id stage)
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{
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uint32_t mixer_cfg = 0;
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switch (pipe) {
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case VG1:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
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break;
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case VG2:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
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break;
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case RGB1:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
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break;
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case RGB2:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
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break;
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case RGB3:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
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break;
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case VG3:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
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break;
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case VG4:
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mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
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break;
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default:
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WARN_ON("invalid pipe");
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break;
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}
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return mixer_cfg;
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}
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int mdp4_disable(struct mdp4_kms *mdp4_kms);
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int mdp4_enable(struct mdp4_kms *mdp4_kms);
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void mdp4_irq_preinstall(struct msm_kms *kms);
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int mdp4_irq_postinstall(struct msm_kms *kms);
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void mdp4_irq_uninstall(struct msm_kms *kms);
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irqreturn_t mdp4_irq(struct msm_kms *kms);
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void mdp4_irq_wait(struct mdp4_kms *mdp4_kms, uint32_t irqmask);
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void mdp4_irq_register(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
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void mdp4_irq_unregister(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
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int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *formats,
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uint32_t max_formats);
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const struct msm_format *mdp4_get_format(struct msm_kms *kms, uint32_t format);
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void mdp4_plane_install_properties(struct drm_plane *plane,
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struct drm_mode_object *obj);
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void mdp4_plane_set_scanout(struct drm_plane *plane,
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struct drm_framebuffer *fb);
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int mdp4_plane_mode_set(struct drm_plane *plane,
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struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h);
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enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
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struct drm_plane *mdp4_plane_init(struct drm_device *dev,
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enum mdp4_pipe pipe_id, bool private_plane);
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uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
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void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc);
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void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
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void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
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void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
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void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
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struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
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struct drm_plane *plane, int id, int ovlp_id,
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enum mdp4_dma dma_id);
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long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
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struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
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#ifdef CONFIG_MSM_BUS_SCALING
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static inline int match_dev_name(struct device *dev, void *data)
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{
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return !strcmp(dev_name(dev), data);
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}
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/* bus scaling data is associated with extra pointless platform devices,
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* "dtv", etc.. this is a bit of a hack, but we need a way for encoders
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* to find their pdata to make the bus-scaling stuff work.
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*/
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static inline void *mdp4_find_pdata(const char *devname)
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{
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struct device *dev;
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dev = bus_find_device(&platform_bus_type, NULL,
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(void *)devname, match_dev_name);
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return dev ? dev->platform_data : NULL;
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}
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#endif
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#endif /* __MDP4_KMS_H__ */
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