Guo Ren dc6fcba72f riscv: Fixup obvious bug for fp-regs reset ... CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by: Guo Ren <ren_guo@c-sky.com> [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e80635619 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2020-01-12 10:12:44 -08:00
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boot	riscv: dts: Add DT support for SiFive L2 cache controller	2020-01-03 00:56:23 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
kernel	riscv: Fixup obvious bug for fp-regs reset	2020-01-12 10:12:44 -08:00
lib	riscv: fix compile failure with EXPORT_SYMBOL() & !MMU	2019-12-27 21:44:36 -08:00
mm	riscv: mm: use __pa_symbol for kernel symbols	2020-01-03 00:33:34 -08:00
net	bpf, riscv: Limit to 33 tail calls	2019-12-11 13:57:17 +01:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: gcov: enable gcov for RISC-V	2020-01-03 00:47:02 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00