Paul Handrigan cadf2120ff ASoC: cs42l73: If Internal MCLK is >= 6.4MHz, then set SCLK to 64*Fs. ...

Signed-off-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

2013-03-06 12:51:30 +08:00

43 KiB

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