Dmitry Osipenko d80a32fe98 clk: tegra: Bump SCLK clock rate to 216 MHz ... AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2017-11-01 15:00:05 +01:00
..
clk-audio-sync.c	clk: tegra: Remove CLK_IS_ROOT	2016-03-02 17:47:19 -08:00
clk-bpmp.c	clk: tegra: Check BPMP response return code	2017-10-19 16:38:40 +02:00
clk-dfll.c	PM / OPP: Update OPP users to put reference	2017-01-30 09:22:21 +01:00
clk-dfll.h	clk: tegra: dfll: Properly clean up on failure and removal	2016-04-28 12:41:54 +02:00
clk-divider.c	tegra/clk-divider: fix wrong do_div() usage	2015-11-16 12:37:55 -05:00
clk-emc.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-id.h	clk: tegra: Add AHB DMA clock entry	2017-11-01 15:00:04 +01:00
clk-periph-fixed.c	clk: tegra: Add fixed factor peripheral clock type	2016-04-28 12:41:47 +02:00
clk-periph-gate.c	clk: tegra: Fix disable unused for clocks sharing enable bit	2017-03-20 14:13:52 +01:00
clk-periph.c	clk: tegra: Add peripheral clock registration helper	2017-10-19 16:38:40 +02:00
clk-pll-out.c	clk: tegra: Properly include clk.h	2015-07-20 11:11:17 -07:00
clk-pll.c	clk: tegra: Fix T210 PLLRE registration	2017-08-23 16:00:23 -07:00
clk-super.c	clk: tegra: Add super clock mux/divider	2017-03-20 14:07:33 +01:00
clk-tegra20.c	clk: tegra: Bump SCLK clock rate to 216 MHz	2017-11-01 15:00:05 +01:00
clk-tegra30.c	clk: tegra: Add AHB DMA clock entry	2017-11-01 15:00:04 +01:00
clk-tegra114.c	clk: tegra: Use tegra_clk_register_periph_data()	2017-10-19 16:38:41 +02:00
clk-tegra124-dfll-fcpu.c	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	2016-11-10 14:08:46 -08:00
clk-tegra124.c	clk: tegra: Add CEC clock	2017-03-20 14:06:23 +01:00
clk-tegra210.c	clk: tegra: Fix sor1_out clock implementation	2017-10-19 16:38:41 +02:00
clk-tegra-audio.c	clk: tegra: Define Tegra210 DMIC sync clocks	2017-03-20 14:06:33 +01:00
clk-tegra-fixed.c	clk: tegra: Remove trailing blank line	2016-04-28 12:41:45 +02:00
clk-tegra-periph.c	clk: tegra: Correct parent of the APBDMA clock	2017-11-01 15:00:04 +01:00
clk-tegra-pmc.c	clk: tegra: Propagate clk_out_x rate to parent	2017-04-04 16:00:28 +02:00
clk-tegra-super-gen4.c	clk: tegra: Mark APB clock as critical	2017-11-01 14:58:13 +01:00
clk.c	clk: tegra: Implement reset control reset	2017-03-20 14:15:31 +01:00
clk.h	clk: tegra: Add peripheral clock registration helper	2017-10-19 16:38:40 +02:00
cvb.c	clk: tegra: dfll: improve function-level documentation	2016-11-01 17:38:50 -07:00
cvb.h	clk: tegra: dfll: Properly clean up on failure and removal	2016-04-28 12:41:54 +02:00
Kconfig	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00
Makefile	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00