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clk: tegra: Correct parent of the APBDMA clock

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APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2017-10-04 02:02:39 +03:00 committed by Thierry Reding
parent 899f8095e6
commit 3ff46fd0b2
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/tegra/clk-tegra-periph.c
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@ -808,7 +808,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),