Alexandre Courbot cfd044b028 drm/nouveau/falcon: fix base address of FBIF registers ... All falcons have their FBIF registers starting at offset 0x600, with the exception of the PMU and NVENC engines. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2017-03-07 17:05:13 +10:00
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base.c	drm/nouveau/falcon: better detection of debug register	2017-03-07 17:05:13 +10:00
Kbuild	drm/nouveau/falcon: support for gm20b msgqueue	2017-03-07 17:05:12 +10:00
msgqueue_0137c63d.c	drm/nouveau/falcon: support for gm20b msgqueue	2017-03-07 17:05:12 +10:00
msgqueue.c	drm/nouveau/falcon: support for gm20b msgqueue	2017-03-07 17:05:12 +10:00
msgqueue.h	drm/nouveau/falcon: support for gm20b msgqueue	2017-03-07 17:05:12 +10:00
priv.h
v1.c	drm/nouveau/falcon: fix base address of FBIF registers	2017-03-07 17:05:13 +10:00