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cfd044b028
linux/drivers/gpu/drm/nouveau/nvkm
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Alexandre Courbot cfd044b028 drm/nouveau/falcon: fix base address of FBIF registers 
All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
..
core drm/nouveau/core: add SEC2 engine 2017-03-07 17:05:13 +10:00
engine drm/nouveau/core: add SEC2 engine 2017-03-07 17:05:13 +10:00
falcon drm/nouveau/falcon: fix base address of FBIF registers 2017-03-07 17:05:13 +10:00
subdev drm/nouveau/core: add SEC2 engine 2017-03-07 17:05:13 +10:00
Kbuild drm/nouveau/core: add falcon library functions 2017-02-17 15:14:30 +10:00