Sowjanya Komatineni 8889398633 dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM ...

Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

2021-01-27 00:10:14 +01:00

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