forked from Minki/linux
c2bf1fc212
Currently Linux does not follow PCIe spec regarding the required delays after reset. A concrete example is a Thunderbolt add-in-card that consists of a PCIe switch and two PCIe endpoints: +-1b.0-[01-6b]----00.0-[02-6b]--+-00.0-[03]----00.0 TBT controller +-01.0-[04-36]-- DS hotplug port +-02.0-[37]----00.0 xHCI controller \-04.0-[38-6b]-- DS hotplug port The root port (1b.0) and the PCIe switch downstream ports are all PCIe gen3 so they support 8GT/s link speeds. We wait for the PCIe hierarchy to enter D3cold (runtime): pcieport 0000:00:1b.0: power state changed by ACPI to D3cold When it wakes up from D3cold, according to the PCIe 4.0 section 5.8 the PCIe switch is put to reset and its power is re-applied. This means that we must follow the rules in PCIe 4.0 section 6.6.1. For the PCIe gen3 ports we are dealing with here, the following applies: With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port. Software can determine when Link training completes by polling the Data Link Layer Link Active bit or by setting up an associated interrupt (see Section 6.7.3.3). Translating this into the above topology we would need to do this (DLLLA stands for Data Link Layer Link Active): pcieport 0000:00:1b.0: wait for 100ms after DLLLA is set before access to 0000:01:00.0 pcieport 0000:02:00.0: wait for 100ms after DLLLA is set before access to 0000:03:00.0 pcieport 0000:02:02.0: wait for 100ms after DLLLA is set before access to 0000:37:00.0 I've instrumented the kernel with additional logging so we can see the actual delays the kernel performs: pcieport 0000:00:1b.0: power state changed by ACPI to D0 pcieport 0000:00:1b.0: waiting for D3cold delay of 100 ms pcieport 0000:00:1b.0: waking up bus pcieport 0000:00:1b.0: waiting for D3hot delay of 10 ms pcieport 0000:00:1b.0: restoring config space at offset 0x2c (was 0x60, writing 0x60) ... pcieport 0000:00:1b.0: PME# disabled pcieport 0000:01:00.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:01:00.0: PME# disabled pcieport 0000:02:00.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:02:00.0: PME# disabled pcieport 0000:02:01.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:02:01.0: restoring config space at offset 0x4 (was 0x100000, writing 0x100407) pcieport 0000:02:01.0: PME# disabled pcieport 0000:02:02.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:02:02.0: PME# disabled pcieport 0000:02:04.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:02:04.0: PME# disabled pcieport 0000:02:01.0: PME# enabled pcieport 0000:02:01.0: waiting for D3hot delay of 10 ms pcieport 0000:02:04.0: PME# enabled pcieport 0000:02:04.0: waiting for D3hot delay of 10 ms thunderbolt 0000:03:00.0: restoring config space at offset 0x14 (was 0x0, writing 0x8a040000) ... thunderbolt 0000:03:00.0: PME# disabled xhci_hcd 0000:37:00.0: restoring config space at offset 0x10 (was 0x0, writing 0x73f00000) ... xhci_hcd 0000:37:00.0: PME# disabled For the switch upstream port (01:00.0) we wait for 100ms but not taking into account the DLLLA requirement. We then wait 10ms for D3hot -> D0 transition of the root port and the two downstream hotplug ports. This means that we deviate from what the spec requires. Performing the same check for system sleep (s2idle) transitions we can see following when resuming from s2idle: pcieport 0000:00:1b.0: power state changed by ACPI to D0 pcieport 0000:00:1b.0: restoring config space at offset 0x2c (was 0x60, writing 0x60) ... pcieport 0000:01:00.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) ... pcieport 0000:02:02.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) pcieport 0000:02:02.0: restoring config space at offset 0x2c (was 0x0, writing 0x0) pcieport 0000:02:01.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) pcieport 0000:02:04.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) pcieport 0000:02:02.0: restoring config space at offset 0x28 (was 0x0, writing 0x0) pcieport 0000:02:00.0: restoring config space at offset 0x3c (was 0x1ff, writing 0x201ff) pcieport 0000:02:02.0: restoring config space at offset 0x24 (was 0x10001, writing 0x1fff1) pcieport 0000:02:01.0: restoring config space at offset 0x2c (was 0x0, writing 0x60) pcieport 0000:02:02.0: restoring config space at offset 0x20 (was 0x0, writing 0x73f073f0) pcieport 0000:02:04.0: restoring config space at offset 0x2c (was 0x0, writing 0x60) pcieport 0000:02:01.0: restoring config space at offset 0x28 (was 0x0, writing 0x60) pcieport 0000:02:00.0: restoring config space at offset 0x2c (was 0x0, writing 0x0) pcieport 0000:02:02.0: restoring config space at offset 0x1c (was 0x101, writing 0x1f1) pcieport 0000:02:04.0: restoring config space at offset 0x28 (was 0x0, writing 0x60) pcieport 0000:02:01.0: restoring config space at offset 0x24 (was 0x10001, writing 0x1ff10001) pcieport 0000:02:00.0: restoring config space at offset 0x28 (was 0x0, writing 0x0) pcieport 0000:02:02.0: restoring config space at offset 0x18 (was 0x0, writing 0x373702) pcieport 0000:02:04.0: restoring config space at offset 0x24 (was 0x10001, writing 0x49f12001) pcieport 0000:02:01.0: restoring config space at offset 0x20 (was 0x0, writing 0x73e05c00) pcieport 0000:02:00.0: restoring config space at offset 0x24 (was 0x10001, writing 0x1fff1) pcieport 0000:02:04.0: restoring config space at offset 0x20 (was 0x0, writing 0x89f07400) pcieport 0000:02:01.0: restoring config space at offset 0x1c (was 0x101, writing 0x5151) pcieport 0000:02:00.0: restoring config space at offset 0x20 (was 0x0, writing 0x8a008a00) pcieport 0000:02:02.0: restoring config space at offset 0xc (was 0x10000, writing 0x10020) pcieport 0000:02:04.0: restoring config space at offset 0x1c (was 0x101, writing 0x6161) pcieport 0000:02:01.0: restoring config space at offset 0x18 (was 0x0, writing 0x360402) pcieport 0000:02:00.0: restoring config space at offset 0x1c (was 0x101, writing 0x1f1) pcieport 0000:02:04.0: restoring config space at offset 0x18 (was 0x0, writing 0x6b3802) pcieport 0000:02:02.0: restoring config space at offset 0x4 (was 0x100000, writing 0x100407) pcieport 0000:02:00.0: restoring config space at offset 0x18 (was 0x0, writing 0x30302) pcieport 0000:02:01.0: restoring config space at offset 0xc (was 0x10000, writing 0x10020) pcieport 0000:02:04.0: restoring config space at offset 0xc (was 0x10000, writing 0x10020) pcieport 0000:02:00.0: restoring config space at offset 0xc (was 0x10000, writing 0x10020) pcieport 0000:02:01.0: restoring config space at offset 0x4 (was 0x100000, writing 0x100407) pcieport 0000:02:04.0: restoring config space at offset 0x4 (was 0x100000, writing 0x100407) pcieport 0000:02:00.0: restoring config space at offset 0x4 (was 0x100000, writing 0x100407) xhci_hcd 0000:37:00.0: restoring config space at offset 0x10 (was 0x0, writing 0x73f00000) ... thunderbolt 0000:03:00.0: restoring config space at offset 0x14 (was 0x0, writing 0x8a040000) This is even worse. None of the mandatory delays are performed. If this would be S3 instead of s2idle then according to PCI FW spec 3.2 section 4.6.8. there is a specific _DSM that allows the OS to skip the delays but this platform does not provide the _DSM and does not go to S3 anyway so no firmware is involved that could already handle these delays. In this particular Intel Coffee Lake platform these delays are not actually needed because there is an additional delay as part of the ACPI power resource that is used to turn on power to the hierarchy but since that additional delay is not required by any of standards (PCIe, ACPI) it is not present in the Intel Ice Lake, for example where missing the mandatory delays causes pciehp to start tearing down the stack too early (links are not yet trained). For this reason, change the PCIe portdrv PM resume hooks so that they perform the mandatory delays before the downstream component gets resumed. We perform the delays before port services are resumed because otherwise pciehp might find that the link is not up (even if it is just training) and tears-down the hierarchy. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
674 lines
18 KiB
C
674 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Purpose: PCI Express Port Bus Driver's Core Functions
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/aer.h>
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#include "../pci.h"
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#include "portdrv.h"
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struct portdrv_service_data {
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struct pcie_port_service_driver *drv;
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struct device *dev;
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u32 service;
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};
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/**
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* release_pcie_device - free PCI Express port service device structure
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* @dev: Port service device to release
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*
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* Invoked automatically when device is being removed in response to
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* device_unregister(dev). Release all resources being claimed.
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*/
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static void release_pcie_device(struct device *dev)
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{
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kfree(to_pcie_device(dev));
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}
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/*
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* Fill in *pme, *aer, *dpc with the relevant Interrupt Message Numbers if
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* services are enabled in "mask". Return the number of MSI/MSI-X vectors
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* required to accommodate the largest Message Number.
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*/
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static int pcie_message_numbers(struct pci_dev *dev, int mask,
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u32 *pme, u32 *aer, u32 *dpc)
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{
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u32 nvec = 0, pos;
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u16 reg16;
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/*
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* The Interrupt Message Number indicates which vector is used, i.e.,
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* the MSI-X table entry or the MSI offset between the base Message
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* Data and the generated interrupt message. See PCIe r3.1, sec
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* 7.8.2, 7.10.10, 7.31.2.
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*/
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if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP |
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PCIE_PORT_SERVICE_BWNOTIF)) {
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pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16);
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*pme = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
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nvec = *pme + 1;
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}
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#ifdef CONFIG_PCIEAER
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if (mask & PCIE_PORT_SERVICE_AER) {
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u32 reg32;
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pos = dev->aer_cap;
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if (pos) {
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pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS,
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®32);
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*aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27;
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nvec = max(nvec, *aer + 1);
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}
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}
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#endif
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if (mask & PCIE_PORT_SERVICE_DPC) {
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP,
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®16);
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*dpc = reg16 & PCI_EXP_DPC_IRQ;
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nvec = max(nvec, *dpc + 1);
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}
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}
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return nvec;
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}
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/**
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* pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
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* for given port
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* @dev: PCI Express port to handle
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* @irqs: Array of interrupt vectors to populate
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* @mask: Bitmask of port capabilities returned by get_port_device_capability()
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*
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* Return value: 0 on success, error code on failure
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*/
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static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)
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{
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int nr_entries, nvec, pcie_irq;
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u32 pme = 0, aer = 0, dpc = 0;
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/* Allocate the maximum possible number of MSI/MSI-X vectors */
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nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES,
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PCI_IRQ_MSIX | PCI_IRQ_MSI);
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if (nr_entries < 0)
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return nr_entries;
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/* See how many and which Interrupt Message Numbers we actually use */
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nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc);
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if (nvec > nr_entries) {
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pci_free_irq_vectors(dev);
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return -EIO;
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}
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/*
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* If we allocated more than we need, free them and reallocate fewer.
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*
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* Reallocating may change the specific vectors we get, so
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* pci_irq_vector() must be done *after* the reallocation.
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*
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* If we're using MSI, hardware is *allowed* to change the Interrupt
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* Message Numbers when we free and reallocate the vectors, but we
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* assume it won't because we allocate enough vectors for the
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* biggest Message Number we found.
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*/
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if (nvec != nr_entries) {
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pci_free_irq_vectors(dev);
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nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
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PCI_IRQ_MSIX | PCI_IRQ_MSI);
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if (nr_entries < 0)
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return nr_entries;
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}
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/* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */
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if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP |
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PCIE_PORT_SERVICE_BWNOTIF)) {
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pcie_irq = pci_irq_vector(dev, pme);
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irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pcie_irq;
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irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pcie_irq;
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irqs[PCIE_PORT_SERVICE_BWNOTIF_SHIFT] = pcie_irq;
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}
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if (mask & PCIE_PORT_SERVICE_AER)
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irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, aer);
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if (mask & PCIE_PORT_SERVICE_DPC)
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irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, dpc);
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return 0;
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}
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/**
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* pcie_init_service_irqs - initialize irqs for PCI Express port services
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* @dev: PCI Express port to handle
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* @irqs: Array of irqs to populate
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* @mask: Bitmask of port capabilities returned by get_port_device_capability()
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*
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* Return value: Interrupt mode associated with the port
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*/
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static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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{
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int ret, i;
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for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
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irqs[i] = -1;
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/*
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* If we support PME but can't use MSI/MSI-X for it, we have to
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* fall back to INTx or other interrupts, e.g., a system shared
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* interrupt.
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*/
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if ((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi())
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goto legacy_irq;
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/* Try to use MSI-X or MSI if supported */
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if (pcie_port_enable_irq_vec(dev, irqs, mask) == 0)
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return 0;
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legacy_irq:
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/* fall back to legacy IRQ */
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ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
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if (ret < 0)
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return -ENODEV;
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for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
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irqs[i] = pci_irq_vector(dev, 0);
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return 0;
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}
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/**
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* get_port_device_capability - discover capabilities of a PCI Express port
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* @dev: PCI Express port to examine
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*
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* The capabilities are read from the port's PCI Express configuration registers
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* as described in PCI Express Base Specification 1.0a sections 7.8.2, 7.8.9 and
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* 7.9 - 7.11.
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*
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* Return value: Bitmask of discovered port capabilities
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*/
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static int get_port_device_capability(struct pci_dev *dev)
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{
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struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
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int services = 0;
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if (dev->is_hotplug_bridge &&
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(pcie_ports_native || host->native_pcie_hotplug)) {
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services |= PCIE_PORT_SERVICE_HP;
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/*
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* Disable hot-plug interrupts in case they have been enabled
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* by the BIOS and the hot-plug service driver is not loaded.
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*/
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pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
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}
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#ifdef CONFIG_PCIEAER
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if (dev->aer_cap && pci_aer_available() &&
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(pcie_ports_native || host->native_aer)) {
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services |= PCIE_PORT_SERVICE_AER;
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/*
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* Disable AER on this port in case it's been enabled by the
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* BIOS (the AER service driver will enable it when necessary).
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*/
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pci_disable_pcie_error_reporting(dev);
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}
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#endif
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/*
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* Root ports are capable of generating PME too. Root Complex
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* Event Collectors can also generate PMEs, but we don't handle
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* those yet.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
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(pcie_ports_native || host->native_pme)) {
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services |= PCIE_PORT_SERVICE_PME;
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/*
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* Disable PME interrupt on this port in case it's been enabled
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* by the BIOS (the PME service driver will enable it when
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* necessary).
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*/
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pcie_pme_interrupt_enable(dev, false);
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}
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if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
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pci_aer_available() && services & PCIE_PORT_SERVICE_AER)
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services |= PCIE_PORT_SERVICE_DPC;
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
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pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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services |= PCIE_PORT_SERVICE_BWNOTIF;
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return services;
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}
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/**
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* pcie_device_init - allocate and initialize PCI Express port service device
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* @pdev: PCI Express port to associate the service device with
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* @service: Type of service to associate with the service device
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* @irq: Interrupt vector to associate with the service device
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*/
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static int pcie_device_init(struct pci_dev *pdev, int service, int irq)
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{
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int retval;
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struct pcie_device *pcie;
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struct device *device;
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pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->port = pdev;
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pcie->irq = irq;
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pcie->service = service;
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/* Initialize generic device interface */
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device = &pcie->device;
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device->bus = &pcie_port_bus_type;
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device->release = release_pcie_device; /* callback to free pcie dev */
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dev_set_name(device, "%s:pcie%03x",
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pci_name(pdev),
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get_descriptor_id(pci_pcie_type(pdev), service));
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device->parent = &pdev->dev;
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device_enable_async_suspend(device);
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retval = device_register(device);
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if (retval) {
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put_device(device);
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return retval;
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}
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pm_runtime_no_callbacks(device);
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return 0;
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}
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/**
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* pcie_port_device_register - register PCI Express port
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* @dev: PCI Express port to register
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*
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* Allocate the port extension structure and register services associated with
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* the port.
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*/
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int pcie_port_device_register(struct pci_dev *dev)
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{
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int status, capabilities, i, nr_service;
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int irqs[PCIE_PORT_DEVICE_MAXSERVICES];
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/* Enable PCI Express port device */
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status = pci_enable_device(dev);
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if (status)
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return status;
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/* Get and check PCI Express port services */
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capabilities = get_port_device_capability(dev);
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if (!capabilities)
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return 0;
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pci_set_master(dev);
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/*
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* Initialize service irqs. Don't use service devices that
|
|
* require interrupts if there is no way to generate them.
|
|
* However, some drivers may have a polling mode (e.g. pciehp_poll_mode)
|
|
* that can be used in the absence of irqs. Allow them to determine
|
|
* if that is to be used.
|
|
*/
|
|
status = pcie_init_service_irqs(dev, irqs, capabilities);
|
|
if (status) {
|
|
capabilities &= PCIE_PORT_SERVICE_HP;
|
|
if (!capabilities)
|
|
goto error_disable;
|
|
}
|
|
|
|
/* Allocate child services if any */
|
|
status = -ENODEV;
|
|
nr_service = 0;
|
|
for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
|
|
int service = 1 << i;
|
|
if (!(capabilities & service))
|
|
continue;
|
|
if (!pcie_device_init(dev, service, irqs[i]))
|
|
nr_service++;
|
|
}
|
|
if (!nr_service)
|
|
goto error_cleanup_irqs;
|
|
|
|
return 0;
|
|
|
|
error_cleanup_irqs:
|
|
pci_free_irq_vectors(dev);
|
|
error_disable:
|
|
pci_disable_device(dev);
|
|
return status;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
typedef int (*pcie_pm_callback_t)(struct pcie_device *);
|
|
|
|
static int pm_iter(struct device *dev, void *data)
|
|
{
|
|
struct pcie_port_service_driver *service_driver;
|
|
size_t offset = *(size_t *)data;
|
|
pcie_pm_callback_t cb;
|
|
|
|
if ((dev->bus == &pcie_port_bus_type) && dev->driver) {
|
|
service_driver = to_service_driver(dev->driver);
|
|
cb = *(pcie_pm_callback_t *)((void *)service_driver + offset);
|
|
if (cb)
|
|
return cb(to_pcie_device(dev));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int get_downstream_delay(struct pci_bus *bus)
|
|
{
|
|
struct pci_dev *pdev;
|
|
int min_delay = 100;
|
|
int max_delay = 0;
|
|
|
|
list_for_each_entry(pdev, &bus->devices, bus_list) {
|
|
if (!pdev->imm_ready)
|
|
min_delay = 0;
|
|
else if (pdev->d3cold_delay < min_delay)
|
|
min_delay = pdev->d3cold_delay;
|
|
if (pdev->d3cold_delay > max_delay)
|
|
max_delay = pdev->d3cold_delay;
|
|
}
|
|
|
|
return max(min_delay, max_delay);
|
|
}
|
|
|
|
/*
|
|
* wait_for_downstream_link - Wait for downstream link to establish
|
|
* @pdev: PCIe port whose downstream link is waited
|
|
*
|
|
* Handle delays according to PCIe 4.0 section 6.6.1 before configuration
|
|
* access to the downstream component is permitted.
|
|
*
|
|
* This blocks PCI core resume of the hierarchy below this port until the
|
|
* link is trained. Should be called before resuming port services to
|
|
* prevent pciehp from starting to tear-down the hierarchy too soon.
|
|
*/
|
|
static void wait_for_downstream_link(struct pci_dev *pdev)
|
|
{
|
|
int delay;
|
|
|
|
if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
|
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
|
|
return;
|
|
|
|
if (pci_dev_is_disconnected(pdev))
|
|
return;
|
|
|
|
if (!pdev->subordinate || list_empty(&pdev->subordinate->devices) ||
|
|
!pdev->bridge_d3)
|
|
return;
|
|
|
|
delay = get_downstream_delay(pdev->subordinate);
|
|
if (!delay)
|
|
return;
|
|
|
|
dev_dbg(&pdev->dev, "waiting downstream link for %d ms\n", delay);
|
|
|
|
/*
|
|
* If downstream port does not support speeds greater than 5 GT/s
|
|
* need to wait 100ms. For higher speeds (gen3) we need to wait
|
|
* first for the data link layer to become active.
|
|
*/
|
|
if (pcie_get_speed_cap(pdev) <= PCIE_SPEED_5_0GT)
|
|
msleep(delay);
|
|
else
|
|
pcie_wait_for_link_delay(pdev, true, delay);
|
|
}
|
|
|
|
/**
|
|
* pcie_port_device_suspend - suspend port services associated with a PCIe port
|
|
* @dev: PCI Express port to handle
|
|
*/
|
|
int pcie_port_device_suspend(struct device *dev)
|
|
{
|
|
size_t off = offsetof(struct pcie_port_service_driver, suspend);
|
|
return device_for_each_child(dev, &off, pm_iter);
|
|
}
|
|
|
|
int pcie_port_device_resume_noirq(struct device *dev)
|
|
{
|
|
size_t off = offsetof(struct pcie_port_service_driver, resume_noirq);
|
|
|
|
wait_for_downstream_link(to_pci_dev(dev));
|
|
return device_for_each_child(dev, &off, pm_iter);
|
|
}
|
|
|
|
/**
|
|
* pcie_port_device_resume - resume port services associated with a PCIe port
|
|
* @dev: PCI Express port to handle
|
|
*/
|
|
int pcie_port_device_resume(struct device *dev)
|
|
{
|
|
size_t off = offsetof(struct pcie_port_service_driver, resume);
|
|
return device_for_each_child(dev, &off, pm_iter);
|
|
}
|
|
|
|
/**
|
|
* pcie_port_device_runtime_suspend - runtime suspend port services
|
|
* @dev: PCI Express port to handle
|
|
*/
|
|
int pcie_port_device_runtime_suspend(struct device *dev)
|
|
{
|
|
size_t off = offsetof(struct pcie_port_service_driver, runtime_suspend);
|
|
return device_for_each_child(dev, &off, pm_iter);
|
|
}
|
|
|
|
/**
|
|
* pcie_port_device_runtime_resume - runtime resume port services
|
|
* @dev: PCI Express port to handle
|
|
*/
|
|
int pcie_port_device_runtime_resume(struct device *dev)
|
|
{
|
|
size_t off = offsetof(struct pcie_port_service_driver, runtime_resume);
|
|
|
|
wait_for_downstream_link(to_pci_dev(dev));
|
|
return device_for_each_child(dev, &off, pm_iter);
|
|
}
|
|
#endif /* PM */
|
|
|
|
static int remove_iter(struct device *dev, void *data)
|
|
{
|
|
if (dev->bus == &pcie_port_bus_type)
|
|
device_unregister(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int find_service_iter(struct device *device, void *data)
|
|
{
|
|
struct pcie_port_service_driver *service_driver;
|
|
struct portdrv_service_data *pdrvs;
|
|
u32 service;
|
|
|
|
pdrvs = (struct portdrv_service_data *) data;
|
|
service = pdrvs->service;
|
|
|
|
if (device->bus == &pcie_port_bus_type && device->driver) {
|
|
service_driver = to_service_driver(device->driver);
|
|
if (service_driver->service == service) {
|
|
pdrvs->drv = service_driver;
|
|
pdrvs->dev = device;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_port_find_service - find the service driver
|
|
* @dev: PCI Express port the service is associated with
|
|
* @service: Service to find
|
|
*
|
|
* Find PCI Express port service driver associated with given service
|
|
*/
|
|
struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev,
|
|
u32 service)
|
|
{
|
|
struct pcie_port_service_driver *drv;
|
|
struct portdrv_service_data pdrvs;
|
|
|
|
pdrvs.drv = NULL;
|
|
pdrvs.service = service;
|
|
device_for_each_child(&dev->dev, &pdrvs, find_service_iter);
|
|
|
|
drv = pdrvs.drv;
|
|
return drv;
|
|
}
|
|
|
|
/**
|
|
* pcie_port_find_device - find the struct device
|
|
* @dev: PCI Express port the service is associated with
|
|
* @service: For the service to find
|
|
*
|
|
* Find the struct device associated with given service on a pci_dev
|
|
*/
|
|
struct device *pcie_port_find_device(struct pci_dev *dev,
|
|
u32 service)
|
|
{
|
|
struct device *device;
|
|
struct portdrv_service_data pdrvs;
|
|
|
|
pdrvs.dev = NULL;
|
|
pdrvs.service = service;
|
|
device_for_each_child(&dev->dev, &pdrvs, find_service_iter);
|
|
|
|
device = pdrvs.dev;
|
|
return device;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcie_port_find_device);
|
|
|
|
/**
|
|
* pcie_port_device_remove - unregister PCI Express port service devices
|
|
* @dev: PCI Express port the service devices to unregister are associated with
|
|
*
|
|
* Remove PCI Express port service devices associated with given port and
|
|
* disable MSI-X or MSI for the port.
|
|
*/
|
|
void pcie_port_device_remove(struct pci_dev *dev)
|
|
{
|
|
device_for_each_child(&dev->dev, NULL, remove_iter);
|
|
pci_free_irq_vectors(dev);
|
|
pci_disable_device(dev);
|
|
}
|
|
|
|
/**
|
|
* pcie_port_probe_service - probe driver for given PCI Express port service
|
|
* @dev: PCI Express port service device to probe against
|
|
*
|
|
* If PCI Express port service driver is registered with
|
|
* pcie_port_service_register(), this function will be called by the driver core
|
|
* whenever match is found between the driver and a port service device.
|
|
*/
|
|
static int pcie_port_probe_service(struct device *dev)
|
|
{
|
|
struct pcie_device *pciedev;
|
|
struct pcie_port_service_driver *driver;
|
|
int status;
|
|
|
|
if (!dev || !dev->driver)
|
|
return -ENODEV;
|
|
|
|
driver = to_service_driver(dev->driver);
|
|
if (!driver || !driver->probe)
|
|
return -ENODEV;
|
|
|
|
pciedev = to_pcie_device(dev);
|
|
status = driver->probe(pciedev);
|
|
if (status)
|
|
return status;
|
|
|
|
get_device(dev);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_port_remove_service - detach driver from given PCI Express port service
|
|
* @dev: PCI Express port service device to handle
|
|
*
|
|
* If PCI Express port service driver is registered with
|
|
* pcie_port_service_register(), this function will be called by the driver core
|
|
* when device_unregister() is called for the port service device associated
|
|
* with the driver.
|
|
*/
|
|
static int pcie_port_remove_service(struct device *dev)
|
|
{
|
|
struct pcie_device *pciedev;
|
|
struct pcie_port_service_driver *driver;
|
|
|
|
if (!dev || !dev->driver)
|
|
return 0;
|
|
|
|
pciedev = to_pcie_device(dev);
|
|
driver = to_service_driver(dev->driver);
|
|
if (driver && driver->remove) {
|
|
driver->remove(pciedev);
|
|
put_device(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_port_shutdown_service - shut down given PCI Express port service
|
|
* @dev: PCI Express port service device to handle
|
|
*
|
|
* If PCI Express port service driver is registered with
|
|
* pcie_port_service_register(), this function will be called by the driver core
|
|
* when device_shutdown() is called for the port service device associated
|
|
* with the driver.
|
|
*/
|
|
static void pcie_port_shutdown_service(struct device *dev) {}
|
|
|
|
/**
|
|
* pcie_port_service_register - register PCI Express port service driver
|
|
* @new: PCI Express port service driver to register
|
|
*/
|
|
int pcie_port_service_register(struct pcie_port_service_driver *new)
|
|
{
|
|
if (pcie_ports_disabled)
|
|
return -ENODEV;
|
|
|
|
new->driver.name = new->name;
|
|
new->driver.bus = &pcie_port_bus_type;
|
|
new->driver.probe = pcie_port_probe_service;
|
|
new->driver.remove = pcie_port_remove_service;
|
|
new->driver.shutdown = pcie_port_shutdown_service;
|
|
|
|
return driver_register(&new->driver);
|
|
}
|
|
EXPORT_SYMBOL(pcie_port_service_register);
|
|
|
|
/**
|
|
* pcie_port_service_unregister - unregister PCI Express port service driver
|
|
* @drv: PCI Express port service driver to unregister
|
|
*/
|
|
void pcie_port_service_unregister(struct pcie_port_service_driver *drv)
|
|
{
|
|
driver_unregister(&drv->driver);
|
|
}
|
|
EXPORT_SYMBOL(pcie_port_service_unregister);
|