Heiko Stuebner 9880d4277f clk: rockchip: fix rk3288 cpuclk core dividers ... Commit 0e5bdb3f9f (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9f ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Cc: stable@vger.kernel.org		2014-12-28 23:31:44 +01:00
..
clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-mmc-phase.c	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
clk-pll.c	clk: rockchip: add optional sync to pll rate parameters	2014-11-25 09:57:18 +01:00
clk-rk3188.c	clk: rockchip: fix rk3066 pll lock bit location	2014-12-28 23:30:08 +01:00
clk-rk3288.c	clk: rockchip: fix rk3288 cpuclk core dividers	2014-12-28 23:31:44 +01:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	- clock phase setting capability for the rk3288 mmc clocks	2014-11-28 21:00:16 -08:00
clk.h	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
Makefile	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00