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clk: rockchip: fix rk3288 cpuclk core dividers

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Commit 0e5bdb3f9f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f9f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
This commit is contained in:
Heiko Stuebner 2014-12-18 20:06:57 +01:00
parent 12551f0239
commit 9880d4277f
1 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/clk/rockchip/clk-rk3288.c
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@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
}
static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
};
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {