Zong Li 94f592f0e5 RISC-V: Add the directive for alignment of stvec's value ... The stvec's value must be 4 byte alignment by specification definition. These directives avoid to stvec be set the non-alignment value. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-08-13 08:31:31 -07:00
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configs	RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig	2018-06-11 09:16:24 -07:00
include	clocksource: new RISC-V SBI timer driver	2018-08-13 08:31:31 -07:00
kernel	RISC-V: Add the directive for alignment of stvec's value	2018-08-13 08:31:31 -07:00
lib	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
mm	RISC-V: Add conditional macro for zone of DMA32	2018-07-04 13:53:21 -07:00
Kconfig	RISC-V: Select GENERIC_UCMPDI2 on RV32I	2018-07-04 13:53:33 -07:00
Makefile	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00