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RISC-V: Add the directive for alignment of stvec's value

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The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Zong Li 2018-08-02 23:21:56 +08:00 committed by Palmer Dabbelt
parent 62b0194368
commit 94f592f0e5
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1 changed files with 2 additions and 0 deletions
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arch/riscv/kernel/head.S
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@ -94,6 +94,7 @@ relocate:
or a0, a0, a1
sfence.vma
csrw sptbr, a0
.align 2
1:
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
@ -143,6 +144,7 @@ relocate:
tail smp_callin
#endif
.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi