900f9ac9f1
So far we only provide num_k8_northbridges. This is required in different areas (e.g. L3 cache index disable, GART). But not all AMD CPUs provide a GART. Thus it is useful to split off the GART handling from the generic caching of AMD northbridge misc devices. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160254.GC4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
40 lines
818 B
C
40 lines
818 B
C
#ifndef _ASM_X86_K8_H
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#define _ASM_X86_K8_H
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#include <linux/pci.h>
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extern struct pci_device_id k8_nb_ids[];
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struct bootnode;
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extern int early_is_k8_nb(u32 value);
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extern int cache_k8_northbridges(void);
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extern void k8_flush_garts(void);
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extern int k8_get_nodes(struct bootnode *nodes);
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extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
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extern int k8_scan_nodes(void);
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struct k8_northbridge_info {
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u16 num;
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u8 gart_supported;
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struct pci_dev **nb_misc;
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};
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extern struct k8_northbridge_info k8_northbridges;
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#ifdef CONFIG_K8_NB
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
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}
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#else
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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return NULL;
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}
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#endif
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#endif /* _ASM_X86_K8_H */
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