forked from Minki/linux
x86, k8-gart: Decouple handling of garts and northbridges
So far we only provide num_k8_northbridges. This is required in different areas (e.g. L3 cache index disable, GART). But not all AMD CPUs provide a GART. Thus it is useful to split off the GART handling from the generic caching of AMD northbridge misc devices. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160254.GC4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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3518dd14ca
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@ -7,24 +7,27 @@ extern struct pci_device_id k8_nb_ids[];
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struct bootnode;
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extern int early_is_k8_nb(u32 value);
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extern struct pci_dev **k8_northbridges;
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extern int num_k8_northbridges;
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extern int cache_k8_northbridges(void);
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extern void k8_flush_garts(void);
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extern int k8_get_nodes(struct bootnode *nodes);
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extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
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extern int k8_scan_nodes(void);
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struct k8_northbridge_info {
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u16 num;
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u8 gart_supported;
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struct pci_dev **nb_misc;
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};
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extern struct k8_northbridge_info k8_northbridges;
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#ifdef CONFIG_K8_NB
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extern int num_k8_northbridges;
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
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return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
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}
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#else
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#define num_k8_northbridges 0
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static inline struct pci_dev *node_to_k8_nb_misc(int node)
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{
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@ -369,7 +369,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
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return;
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/* not in virtualized environments */
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if (num_k8_northbridges == 0)
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if (k8_northbridges.num == 0)
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return;
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/*
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@ -377,7 +377,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
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* never freed but this is done only on shutdown so it doesn't matter.
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*/
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if (!l3_caches) {
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int size = num_k8_northbridges * sizeof(struct amd_l3_cache *);
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int size = k8_northbridges.num * sizeof(struct amd_l3_cache *);
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l3_caches = kzalloc(size, GFP_ATOMIC);
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if (!l3_caches)
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@ -10,9 +10,6 @@
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#include <linux/spinlock.h>
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#include <asm/k8.h>
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int num_k8_northbridges;
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EXPORT_SYMBOL(num_k8_northbridges);
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static u32 *flush_words;
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struct pci_device_id k8_nb_ids[] = {
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@ -22,7 +19,7 @@ struct pci_device_id k8_nb_ids[] = {
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};
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EXPORT_SYMBOL(k8_nb_ids);
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struct pci_dev **k8_northbridges;
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struct k8_northbridge_info k8_northbridges;
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EXPORT_SYMBOL(k8_northbridges);
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static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
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@ -40,36 +37,44 @@ int cache_k8_northbridges(void)
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int i;
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struct pci_dev *dev;
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if (num_k8_northbridges)
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if (k8_northbridges.num)
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return 0;
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dev = NULL;
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while ((dev = next_k8_northbridge(dev)) != NULL)
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num_k8_northbridges++;
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k8_northbridges.num++;
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k8_northbridges = kmalloc((num_k8_northbridges + 1) * sizeof(void *),
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GFP_KERNEL);
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if (!k8_northbridges)
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/* some CPU families (e.g. family 0x11) do not support GART */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
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k8_northbridges.gart_supported = 1;
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k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
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sizeof(void *), GFP_KERNEL);
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if (!k8_northbridges.nb_misc)
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return -ENOMEM;
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if (!num_k8_northbridges) {
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k8_northbridges[0] = NULL;
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if (!k8_northbridges.num) {
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k8_northbridges.nb_misc[0] = NULL;
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return 0;
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}
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flush_words = kmalloc(num_k8_northbridges * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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kfree(k8_northbridges);
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return -ENOMEM;
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if (k8_northbridges.gart_supported) {
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flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
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GFP_KERNEL);
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if (!flush_words) {
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kfree(k8_northbridges.nb_misc);
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return -ENOMEM;
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}
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}
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dev = NULL;
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i = 0;
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while ((dev = next_k8_northbridge(dev)) != NULL) {
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k8_northbridges[i] = dev;
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pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
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k8_northbridges.nb_misc[i] = dev;
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if (k8_northbridges.gart_supported)
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pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
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}
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k8_northbridges[i] = NULL;
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k8_northbridges.nb_misc[i] = NULL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cache_k8_northbridges);
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@ -93,22 +98,25 @@ void k8_flush_garts(void)
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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if (!k8_northbridges.gart_supported)
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return;
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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but I'm not sure if the hardware won't lose flush requests
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when another is pending. This whole thing is so expensive anyways
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < num_k8_northbridges; i++) {
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pci_write_config_dword(k8_northbridges[i], 0x9c,
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for (i = 0; i < k8_northbridges.num; i++) {
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pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
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flush_words[i]|1);
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flushed++;
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}
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for (i = 0; i < num_k8_northbridges; i++) {
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for (i = 0; i < k8_northbridges.num; i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(k8_northbridges[i],
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pci_read_config_dword(k8_northbridges.nb_misc[i],
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0x9c, &w);
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if (!(w & 1))
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break;
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@ -560,8 +560,11 @@ static void enable_gart_translations(void)
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{
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int i;
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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if (!k8_northbridges.gart_supported)
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return;
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for (i = 0; i < k8_northbridges.num; i++) {
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struct pci_dev *dev = k8_northbridges.nb_misc[i];
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enable_gart_translation(dev, __pa(agp_gatt_table));
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}
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@ -592,10 +595,13 @@ static void gart_fixup_northbridges(struct sys_device *dev)
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if (!fix_up_north_bridges)
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return;
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if (!k8_northbridges.gart_supported)
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return;
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pr_info("PCI-DMA: Restoring GART aperture settings\n");
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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for (i = 0; i < k8_northbridges.num; i++) {
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struct pci_dev *dev = k8_northbridges.nb_misc[i];
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/*
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* Don't enable translations just yet. That is the next
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@ -649,8 +655,8 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
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aper_size = aper_base = info->aper_size = 0;
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dev = NULL;
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for (i = 0; i < num_k8_northbridges; i++) {
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dev = k8_northbridges[i];
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for (i = 0; i < k8_northbridges.num; i++) {
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dev = k8_northbridges.nb_misc[i];
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new_aper_base = read_aperture(dev, &new_aper_size);
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if (!new_aper_base)
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goto nommu;
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@ -718,10 +724,13 @@ static void gart_iommu_shutdown(void)
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if (!no_agp)
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return;
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for (i = 0; i < num_k8_northbridges; i++) {
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if (!k8_northbridges.gart_supported)
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return;
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for (i = 0; i < k8_northbridges.num; i++) {
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u32 ctl;
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dev = k8_northbridges[i];
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dev = k8_northbridges.nb_misc[i];
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
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ctl &= ~GARTEN;
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@ -739,7 +748,7 @@ int __init gart_iommu_init(void)
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unsigned long scratch;
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long i;
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if (num_k8_northbridges == 0)
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if (!k8_northbridges.gart_supported)
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return 0;
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#ifndef CONFIG_AGP_AMD64
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@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
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u32 temp;
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struct aper_size_info_32 *values;
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dev = k8_northbridges[0];
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dev = k8_northbridges.nb_misc[0];
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if (dev==NULL)
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return 0;
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@ -181,10 +181,14 @@ static int amd_8151_configure(void)
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unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
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int i;
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if (!k8_northbridges.gart_supported)
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return 0;
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/* Configure AGP regs in each x86-64 host bridge. */
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for (i = 0; i < num_k8_northbridges; i++) {
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for (i = 0; i < k8_northbridges.num; i++) {
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agp_bridge->gart_bus_addr =
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amd64_configure(k8_northbridges[i], gatt_bus);
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amd64_configure(k8_northbridges.nb_misc[i],
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gatt_bus);
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}
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k8_flush_garts();
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return 0;
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@ -195,8 +199,12 @@ static void amd64_cleanup(void)
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{
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u32 tmp;
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int i;
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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if (!k8_northbridges.gart_supported)
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return;
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for (i = 0; i < k8_northbridges.num; i++) {
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struct pci_dev *dev = k8_northbridges.nb_misc[i];
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/* disable gart translation */
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
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tmp &= ~AMD64_GARTEN;
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@ -319,16 +327,19 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
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return 0;
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}
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static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
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static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
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{
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int i;
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if (cache_k8_northbridges() < 0)
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return -ENODEV;
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if (!k8_northbridges.gart_supported)
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return -ENODEV;
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i = 0;
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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for (i = 0; i < k8_northbridges.num; i++) {
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struct pci_dev *dev = k8_northbridges.nb_misc[i];
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if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
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dev_err(&dev->dev, "no usable aperture found\n");
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#ifdef __x86_64__
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@ -405,7 +416,8 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
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}
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/* shadow x86-64 registers into ULi registers */
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pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
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pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
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&httfea);
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/* if x86-64 aperture base is beyond 4G, exit here */
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if ((httfea & 0x7fff) >> (32 - 25)) {
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@ -472,7 +484,8 @@ static int nforce3_agp_init(struct pci_dev *pdev)
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pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
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/* shadow x86-64 registers into NVIDIA registers */
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pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
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pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
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&apbase);
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/* if x86-64 aperture base is beyond 4G, exit here */
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if ( (apbase & 0x7fff) >> (32 - 25) ) {
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@ -2927,7 +2927,7 @@ static int __init amd64_edac_init(void)
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* to finish initialization of the MC instances.
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*/
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err = -ENODEV;
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for (nb = 0; nb < num_k8_northbridges; nb++) {
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for (nb = 0; nb < k8_northbridges.num; nb++) {
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if (!pvt_lookup[nb])
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continue;
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