8c1aeaa139
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
128 lines
3.6 KiB
C
128 lines
3.6 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv40.h"
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static void
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nv40_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
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struct nvkm_perfctr *ctr)
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{
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struct nv40_pm_cntr *cntr = (void *)ctr;
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u32 log = ctr->logic_op;
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u32 src = 0x00000000;
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int i;
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for (i = 0; i < 4; i++)
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src |= ctr->signal[i] << (i * 8);
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nv_wr32(pm, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4));
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nv_wr32(pm, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
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nv_wr32(pm, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
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}
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static void
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nv40_perfctr_read(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
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struct nvkm_perfctr *ctr)
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{
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struct nv40_pm_cntr *cntr = (void *)ctr;
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switch (cntr->base.slot) {
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case 0: cntr->base.ctr = nv_rd32(pm, 0x00a700 + dom->addr); break;
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case 1: cntr->base.ctr = nv_rd32(pm, 0x00a6c0 + dom->addr); break;
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case 2: cntr->base.ctr = nv_rd32(pm, 0x00a680 + dom->addr); break;
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case 3: cntr->base.ctr = nv_rd32(pm, 0x00a740 + dom->addr); break;
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}
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dom->clk = nv_rd32(pm, 0x00a600 + dom->addr);
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}
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static void
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nv40_perfctr_next(struct nvkm_pm *pm, struct nvkm_perfdom *dom)
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{
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if (pm->sequence != pm->sequence) {
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nv_wr32(pm, 0x400084, 0x00000020);
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pm->sequence = pm->sequence;
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}
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}
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const struct nvkm_funcdom
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nv40_perfctr_func = {
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.init = nv40_perfctr_init,
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.read = nv40_perfctr_read,
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.next = nv40_perfctr_next,
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};
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static const struct nvkm_specdom
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nv40_pm[] = {
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{ 0x20, (const struct nvkm_specsig[]) {
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{}
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}, &nv40_perfctr_func },
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{ 0x20, (const struct nvkm_specsig[]) {
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{}
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}, &nv40_perfctr_func },
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{ 0x20, (const struct nvkm_specsig[]) {
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{}
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}, &nv40_perfctr_func },
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{ 0x20, (const struct nvkm_specsig[]) {
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{}
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}, &nv40_perfctr_func },
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{ 0x20, (const struct nvkm_specsig[]) {
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{}
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}, &nv40_perfctr_func },
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{}
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};
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int
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nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv40_pm_oclass *mclass = (void *)oclass;
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struct nv40_pm *pm;
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int ret;
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ret = nvkm_pm_create(parent, engine, oclass, &pm);
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*pobject = nv_object(pm);
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if (ret)
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return ret;
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ret = nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, mclass->doms);
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if (ret)
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return ret;
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nv_engine(pm)->cclass = &nvkm_pm_cclass;
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nv_engine(pm)->sclass = nvkm_pm_sclass;
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return 0;
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}
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struct nvkm_oclass *
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nv40_pm_oclass = &(struct nv40_pm_oclass) {
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.base.handle = NV_ENGINE(PM, 0x40),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv40_pm_ctor,
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.dtor = _nvkm_pm_dtor,
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.init = _nvkm_pm_init,
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.fini = _nvkm_pm_fini,
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},
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.doms = nv40_pm,
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}.base;
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