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Processors with coherent icache require the sequence sync ; icbi ; isync to entire store->execute coherency. icbi (to any address) must be executed to ensure isync flushes the pipeline. See "POWER9 Processor User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for details. __kernel_sync_dicache is missing icbi for the coherent icache path. Add it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220520123649.258440-1-npiggin@gmail.com |
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| .. | ||
| .gitignore | ||
| cacheflush.S | ||
| datapage.S | ||
| gen_vdso32_offsets.sh | ||
| gen_vdso64_offsets.sh | ||
| getcpu.S | ||
| gettimeofday.S | ||
| Makefile | ||
| note.S | ||
| sigtramp32.S | ||
| sigtramp64.S | ||
| vdso32.lds.S | ||
| vdso64.lds.S | ||
| vgettimeofday.c | ||