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powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache

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Processors with coherent icache require the sequence sync ; icbi ; isync
to entire store->execute coherency. icbi (to any address) must be
executed to ensure isync flushes the pipeline. See "POWER9 Processor
User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for
details.

__kernel_sync_dicache is missing icbi for the coherent icache path.
Add it.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220520123649.258440-1-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin 2022-05-20 22:36:49 +10:00 committed by Michael Ellerman
parent 5663568130
commit 28f07fab26
1 changed files with 1 additions and 0 deletions
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arch/powerpc/kernel/vdso/cacheflush.S
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@ -91,6 +91,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
3:
crclr cr0*4+so
sync
icbi 0,r1
isync
li r3,0
blr