bd68fb94b3
iterate over all error counter registers in SMN space removed support error counter access via MMIO Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
59 lines
2.4 KiB
C
59 lines
2.4 KiB
C
/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_UMC_H__
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#define __AMDGPU_UMC_H__
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struct amdgpu_umc_funcs {
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void (*err_cnt_init)(struct amdgpu_device *adev);
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int (*ras_late_init)(struct amdgpu_device *adev);
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void (*query_ras_error_count)(struct amdgpu_device *adev,
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void *ras_error_status);
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void (*query_ras_error_address)(struct amdgpu_device *adev,
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void *ras_error_status);
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void (*init_registers)(struct amdgpu_device *adev);
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};
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struct amdgpu_umc {
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/* max error count in one ras query call */
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uint32_t max_ras_err_cnt_per_query;
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/* number of umc channel instance with memory map register access */
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uint32_t channel_inst_num;
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/* number of umc instance with memory map register access */
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uint32_t umc_inst_num;
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/* UMC regiser per channel offset */
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uint32_t channel_offs;
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/* channel index table of interleaved memory */
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const uint32_t *channel_idx_tbl;
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struct ras_common_if *ras_if;
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const struct amdgpu_umc_funcs *funcs;
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};
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int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
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void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
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int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
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void *ras_error_status,
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struct amdgpu_iv_entry *entry);
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int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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#endif
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