drm/amdgpu: resolve bug in UMC 6 error counter query
iterate over all error counter registers in SMN space removed support error counter access via MMIO Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
John Clements
Alex Deucher
parent
a210d69872
commit
bd68fb94b3
@ -21,38 +21,6 @@
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#ifndef __AMDGPU_UMC_H__
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#define __AMDGPU_UMC_H__
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/* implement 64 bits REG operations via 32 bits interface */
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#define RREG64_UMC(reg) (RREG32(reg) | \
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((uint64_t)RREG32((reg) + 1) << 32))
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#define WREG64_UMC(reg, v) \
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do { \
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WREG32((reg), lower_32_bits(v)); \
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WREG32((reg) + 1, upper_32_bits(v)); \
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} while (0)
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/*
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* void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
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* uint32_t umc_reg_offset, uint32_t channel_index)
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*/
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#define amdgpu_umc_for_each_channel(func) \
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; \
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uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \
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for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) { \
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/* enable the index mode to query eror count per channel */ \
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adev->umc.funcs->enable_umc_index_mode(adev, umc_inst); \
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for (channel_inst = 0; \
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channel_inst < adev->umc.channel_inst_num; \
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channel_inst++) { \
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/* calc the register offset according to channel instance */ \
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umc_reg_offset = adev->umc.channel_offs * channel_inst; \
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/* get channel index of interleaved memory */ \
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channel_index = adev->umc.channel_idx_tbl[ \
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umc_inst * adev->umc.channel_inst_num + channel_inst]; \
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(func)(adev, err_data, umc_reg_offset, channel_index); \
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} \
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} \
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adev->umc.funcs->disable_umc_index_mode(adev);
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struct amdgpu_umc_funcs {
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void (*err_cnt_init)(struct amdgpu_device *adev);
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int (*ras_late_init)(struct amdgpu_device *adev);
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@ -60,9 +28,6 @@ struct amdgpu_umc_funcs {
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void *ras_error_status);
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void (*query_ras_error_address)(struct amdgpu_device *adev,
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void *ras_error_status);
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void (*enable_umc_index_mode)(struct amdgpu_device *adev,
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uint32_t umc_instance);
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void (*disable_umc_index_mode)(struct amdgpu_device *adev);
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void (*init_registers)(struct amdgpu_device *adev);
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};
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@ -32,11 +32,13 @@
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#define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10
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#define UMC_6_INST_DIST 0x40000
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/*
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* (addr / 256) * 8192, the higher 26 bits in ErrorAddr
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* is the index of 8KB block
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*/
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#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
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#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
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/* channel index is the index of 256B block */
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#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8)
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/* offset in 256B block */
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@ -50,41 +52,11 @@ const uint32_t
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{9, 25, 0, 16}, {15, 31, 6, 22}
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};
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static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
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uint32_t umc_instance)
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static inline uint32_t get_umc_6_reg_offset(struct amdgpu_device *adev,
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uint32_t umc_inst,
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uint32_t ch_inst)
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{
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uint32_t rsmu_umc_index;
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rsmu_umc_index = RREG32_SOC15(RSMU, 0,
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mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 1);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_INSTANCE, umc_instance);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_WREN, 1 << umc_instance);
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WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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rsmu_umc_index);
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}
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static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
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{
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WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 0);
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}
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static uint32_t umc_v6_1_get_umc_inst(struct amdgpu_device *adev)
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{
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uint32_t rsmu_umc_index;
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rsmu_umc_index = RREG32_SOC15(RSMU, 0,
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mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
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return REG_GET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_INSTANCE);
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return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst;
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}
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static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
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@ -174,25 +146,36 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
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*error_count += 1;
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}
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static void umc_v6_1_query_error_count(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint32_t umc_reg_offset,
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uint32_t channel_index)
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{
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umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
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&(err_data->ce_count));
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umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
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&(err_data->ue_count));
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}
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static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_for_each_channel(umc_v6_1_query_error_count);
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struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {
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for (ch_inst = 0; ch_inst < adev->umc.channel_inst_num; ch_inst++) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
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ch_inst);
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umc_v6_1_query_correctable_error_count(adev,
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umc_reg_offset,
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&(err_data->ce_count));
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umc_v6_1_querry_uncorrectable_error_count(adev,
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umc_reg_offset,
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&(err_data->ue_count));
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}
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}
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}
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static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t umc_reg_offset, uint32_t channel_index)
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uint32_t umc_reg_offset,
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uint32_t channel_index,
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uint32_t umc_inst)
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{
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uint32_t lsb, mc_umc_status_addr;
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uint64_t mc_umc_status, err_addr, retired_page;
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@ -244,7 +227,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
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err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
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err_rec->cu = 0;
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err_rec->mem_channel = channel_index;
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err_rec->mcumc_id = umc_v6_1_get_umc_inst(adev);
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err_rec->mcumc_id = umc_inst;
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err_data->err_addr_cnt++;
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}
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@ -257,12 +240,30 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
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static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
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struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {
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for (ch_inst = 0; ch_inst < adev->umc.channel_inst_num; ch_inst++) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
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ch_inst);
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umc_v6_1_query_error_address(adev,
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err_data,
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umc_reg_offset,
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ch_inst,
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umc_inst);
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}
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}
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}
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static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t umc_reg_offset, uint32_t channel_index)
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uint32_t umc_reg_offset)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt_addr;
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@ -301,9 +302,19 @@ static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
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static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev)
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{
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void *ras_error_status = NULL;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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amdgpu_umc_for_each_channel(umc_v6_1_err_cnt_init_per_channel);
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for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {
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for (ch_inst = 0; ch_inst < adev->umc.channel_inst_num; ch_inst++) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
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ch_inst);
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umc_v6_1_err_cnt_init_per_channel(adev, umc_reg_offset);
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}
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}
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}
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const struct amdgpu_umc_funcs umc_v6_1_funcs = {
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@ -311,6 +322,4 @@ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
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.ras_late_init = amdgpu_umc_ras_late_init,
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.query_ras_error_count = umc_v6_1_query_ras_error_count,
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.query_ras_error_address = umc_v6_1_query_ras_error_address,
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.enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
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.disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
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};
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