forked from Minki/linux
290622efc7
The ARM errata 819472, 826319, 827319 and 824069 for affected Cortex-A53 cores demand to promote "dc cvau" instructions to "dc civac" as well. Attribute the usage of the instruction in __flush_cache_user_range to also be covered by our alternative patching efforts. For that we introduce an assembly macro which both deals with alternatives while still tagging the instructions as USER. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
213 lines
5.7 KiB
C
213 lines
5.7 KiB
C
#ifndef __ASM_ALTERNATIVE_H
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#define __ASM_ALTERNATIVE_H
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#include <asm/cpufeature.h>
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#ifndef __ASSEMBLY__
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#include <linux/init.h>
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#include <linux/kconfig.h>
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <linux/stringify.h>
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struct alt_instr {
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s32 orig_offset; /* offset to original instruction */
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s32 alt_offset; /* offset to replacement instruction */
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u16 cpufeature; /* cpufeature bit set for replacement */
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u8 orig_len; /* size of original instruction(s) */
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u8 alt_len; /* size of new instruction(s), <= orig_len */
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};
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void __init apply_alternatives_all(void);
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void apply_alternatives(void *start, size_t length);
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#define ALTINSTR_ENTRY(feature) \
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" .word 661b - .\n" /* label */ \
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" .word 663f - .\n" /* new instruction */ \
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" .hword " __stringify(feature) "\n" /* feature bit */ \
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" .byte 662b-661b\n" /* source len */ \
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" .byte 664f-663f\n" /* replacement len */
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/*
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* alternative assembly primitive:
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*
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* If any of these .org directive fail, it means that insn1 and insn2
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* don't have the same length. This used to be written as
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*
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* .if ((664b-663b) != (662b-661b))
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* .error "Alternatives instruction length mismatch"
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* .endif
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*
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* but most assemblers die if insn1 or insn2 have a .inst. This should
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* be fixed in a binutils release posterior to 2.25.51.0.2 (anything
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* containing commit 4e4d08cf7399b606 or c1baaddf8861).
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*/
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#define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled) \
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".if "__stringify(cfg_enabled)" == 1\n" \
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"661:\n\t" \
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oldinstr "\n" \
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"662:\n" \
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".pushsection .altinstructions,\"a\"\n" \
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ALTINSTR_ENTRY(feature) \
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".popsection\n" \
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".pushsection .altinstr_replacement, \"a\"\n" \
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"663:\n\t" \
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newinstr "\n" \
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"664:\n\t" \
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".popsection\n\t" \
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".org . - (664b-663b) + (662b-661b)\n\t" \
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".org . - (662b-661b) + (664b-663b)\n" \
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".endif\n"
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#define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \
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__ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg))
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#else
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#include <asm/assembler.h>
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.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
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.word \orig_offset - .
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.word \alt_offset - .
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.hword \feature
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.byte \orig_len
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.byte \alt_len
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.endm
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.macro alternative_insn insn1, insn2, cap, enable = 1
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.if \enable
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661: \insn1
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662: .pushsection .altinstructions, "a"
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altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
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.popsection
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.pushsection .altinstr_replacement, "ax"
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663: \insn2
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664: .popsection
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.org . - (664b-663b) + (662b-661b)
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.org . - (662b-661b) + (664b-663b)
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.endif
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.endm
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/*
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* Begin an alternative code sequence.
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*
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* The code that follows this macro will be assembled and linked as
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* normal. There are no restrictions on this code.
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*/
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.macro alternative_if_not cap
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.pushsection .altinstructions, "a"
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altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f
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.popsection
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661:
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.endm
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/*
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* Provide the alternative code sequence.
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*
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* The code that follows this macro is assembled into a special
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* section to be used for dynamic patching. Code that follows this
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* macro must:
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*
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* 1. Be exactly the same length (in bytes) as the default code
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* sequence.
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*
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* 2. Not contain a branch target that is used outside of the
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* alternative sequence it is defined in (branches into an
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* alternative sequence are not fixed up).
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*/
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.macro alternative_else
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662: .pushsection .altinstr_replacement, "ax"
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663:
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.endm
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/*
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* Complete an alternative code sequence.
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*/
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.macro alternative_endif
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664: .popsection
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.org . - (664b-663b) + (662b-661b)
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.org . - (662b-661b) + (664b-663b)
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.endm
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#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
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alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
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.macro user_alt, label, oldinstr, newinstr, cond
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9999: alternative_insn "\oldinstr", "\newinstr", \cond
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_ASM_EXTABLE 9999b, \label
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.endm
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/*
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* Generate the assembly for UAO alternatives with exception table entries.
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* This is complicated as there is no post-increment or pair versions of the
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* unprivileged instructions, and USER() only works for single instructions.
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*/
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#ifdef CONFIG_ARM64_UAO
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.macro uao_ldp l, reg1, reg2, addr, post_inc
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alternative_if_not ARM64_HAS_UAO
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8888: ldp \reg1, \reg2, [\addr], \post_inc;
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8889: nop;
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nop;
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alternative_else
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ldtr \reg1, [\addr];
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ldtr \reg2, [\addr, #8];
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add \addr, \addr, \post_inc;
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alternative_endif
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_asm_extable 8888b,\l;
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_asm_extable 8889b,\l;
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.endm
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.macro uao_stp l, reg1, reg2, addr, post_inc
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alternative_if_not ARM64_HAS_UAO
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8888: stp \reg1, \reg2, [\addr], \post_inc;
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8889: nop;
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nop;
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alternative_else
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sttr \reg1, [\addr];
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sttr \reg2, [\addr, #8];
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add \addr, \addr, \post_inc;
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alternative_endif
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_asm_extable 8888b,\l;
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_asm_extable 8889b,\l;
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.endm
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.macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc
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alternative_if_not ARM64_HAS_UAO
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8888: \inst \reg, [\addr], \post_inc;
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nop;
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alternative_else
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\alt_inst \reg, [\addr];
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add \addr, \addr, \post_inc;
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alternative_endif
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_asm_extable 8888b,\l;
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.endm
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#else
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.macro uao_ldp l, reg1, reg2, addr, post_inc
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USER(\l, ldp \reg1, \reg2, [\addr], \post_inc)
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.endm
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.macro uao_stp l, reg1, reg2, addr, post_inc
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USER(\l, stp \reg1, \reg2, [\addr], \post_inc)
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.endm
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.macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc
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USER(\l, \inst \reg, [\addr], \post_inc)
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.endm
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#endif
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#endif /* __ASSEMBLY__ */
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/*
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* Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature));
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*
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* Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO));
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* N.B. If CONFIG_FOO is specified, but not selected, the whole block
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* will be omitted, including oldinstr.
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*/
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#define ALTERNATIVE(oldinstr, newinstr, ...) \
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_ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)
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#endif /* __ASM_ALTERNATIVE_H */
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