forked from Minki/linux
arm64: fix "dc cvau" cache operation on errata-affected core
The ARM errata 819472, 826319, 827319 and 824069 for affected Cortex-A53 cores demand to promote "dc cvau" instructions to "dc civac" as well. Attribute the usage of the instruction in __flush_cache_user_range to also be covered by our alternative patching efforts. For that we introduce an assembly macro which both deals with alternatives while still tagging the instructions as USER. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -133,6 +133,10 @@ void apply_alternatives(void *start, size_t length);
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#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
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alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
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.macro user_alt, label, oldinstr, newinstr, cond
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9999: alternative_insn "\oldinstr", "\newinstr", \cond
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_ASM_EXTABLE 9999b, \label
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.endm
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/*
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* Generate the assembly for UAO alternatives with exception table entries.
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@ -52,7 +52,7 @@ ENTRY(__flush_cache_user_range)
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sub x3, x2, #1
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bic x4, x0, x3
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1:
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USER(9f, dc cvau, x4 ) // clean D line to PoU
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user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
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add x4, x4, x2
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cmp x4, x1
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b.lo 1b
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