linux/drivers/gpu/drm/amd/display/dc/inc
Wesley Chalmers 30adeee52d drm/amd/display: Enforce DPCD Address ranges
[WHY]
Some DPCD addresses, notably LTTPR Capability registers, are expected to
be read all together in a single DPCD transaction. Rather than force callers to
read registers they don't need, we want to quietly extend the addresses
read, and only return back the values the caller asked for.
This does not affect DPCD writes.

[HOW]
Create an additional layer above AUX to perform 'checked' DPCD
transactions.
Iterate through an array of DPCD address ranges that are marked as being
contiguous. If a requested read falls within one of those ranges, extend
the read to include the entire range.
After DPCD has been queried, copy the requested bytes into the caller's
data buffer, and deallocate all resources used.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-15 17:25:41 -04:00
..
hw drm/amd/display: Add interface for ADD & DROP PIXEL Registers 2021-06-08 12:22:42 -04:00
bw_fixed.h
clock_source.h drm/amd/display: Synchronize displays with different timings 2021-02-22 18:05:48 -05:00
compressor.h drm/amd/display: fbc state could not reach while enable fbc 2018-11-30 12:02:35 -05:00
core_status.h drm/amd/display: fail instead of div by zero/bugcheck 2020-11-02 15:30:47 -05:00
core_types.h drm/amd/display: Add DCN3.1 DCHHUB 2021-06-04 16:39:18 -04:00
custom_float.h
dc_link_ddc.h drm/amd/display: Support for DMUB AUX 2021-03-02 14:05:41 -05:00
dc_link_dp.h drm/amd/display: Read LTTPR caps first on bootup 2021-06-15 17:25:41 -04:00
dce_calcs.h
dcn_calc_math.h drm/amd/display: fixup DML dependencies 2020-01-16 14:16:48 -05:00
dcn_calcs.h drm/amd/display: make clk mgr soc specific 2019-05-31 10:39:29 -05:00
hw_sequencer_private.h drm/amd/display: Refactor visual confirm 2021-06-08 12:18:37 -04:00
hw_sequencer.h drm/amd/display: Add swizzle visual confirm mode 2021-06-08 12:24:04 -04:00
link_dpcd.h drm/amd/display: Enforce DPCD Address ranges 2021-06-15 17:25:41 -04:00
link_enc_cfg.h drm/amd/display: Update setting of DP training parameters. 2021-05-10 18:09:53 -04:00
link_hwss.h drm/amd/display: Enforce DPCD Address ranges 2021-06-15 17:25:41 -04:00
reg_helper.h drm/amd/display: Indirect reg read macro with shift and mask 2020-01-16 14:13:53 -05:00
resource.h drm/amd/display: Update link encoder object creation 2021-03-02 14:05:52 -05:00
vm_helper.h drm/amd/display: move vmid determination logic to a module 2019-06-22 09:34:14 -05:00