Wenjing Liu 1cf49dea28 drm/amd/display: do not reset lane count in EQ fallback ... [Description] According to DP1.4 specs we should not reset lane count back when falling back in failing EQ training. This causes PHY test pattern compliance to fail as infinite LT when LT fails EQ to 4 RBR and fails CR in a loop. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-09-26 18:17:08 -04:00
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acp	drm: amd: remove broken include path	2017-03-14 19:19:44 -04:00
amdgpu	drm/amd/display: Enable Vega by default.	2017-09-26 18:16:48 -04:00
amdkfd	drm/amdkfd: Use PASID manager from KGD	2017-09-26 13:07:04 -04:00
display	drm/amd/display: do not reset lane count in EQ fallback	2017-09-26 18:17:08 -04:00
include	drm/amd: Add missing SURFACE_TMZ register shift/mask	2017-09-26 18:15:20 -04:00
lib	drm/amd: Closed hash table with low overhead (v2)	2017-09-26 14:53:19 -04:00
powerplay	drm/amd/powerplay: delete dead code in smumgr	2017-09-26 15:14:36 -04:00
scheduler	drm/amdgpu: discard commands of killed processes	2017-08-29 15:27:42 -04:00