linux/include/soc
Palmer Dabbelt 1a5a2cbd21
Merge patch series "Use composable cache instead of L2 cache"
Zong Li <zong.li@sifive.com> says:

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

* b4-shazam-merge:
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13 11:07:13 -07:00
..
arc clocksource/drivers/arc_timer: Eliminate redefined macro error 2021-10-16 22:15:01 +02:00
at91 ARM: at91: pm: fix DDR recalibration when resuming from backup and self-refresh 2022-08-31 10:28:18 +03:00
bcm2835 firmware: raspberrypi: Add RPI_FIRMWARE_NOTIFY_DISPLAY_DONE 2022-01-11 13:16:10 +01:00
canaan clk: Add RISC-V Canaan Kendryte K210 clock driver 2021-02-22 17:51:04 -08:00
fsl soc: fsl: qbman: Add CGR update function 2022-09-05 14:27:39 +01:00
imx ARM: imx: Initialize SoC ID on i.MX50 2021-05-13 15:42:21 +08:00
mediatek memory: mtk-smi: Add enable IOMMU SMC command for MM master 2022-08-30 20:54:05 +03:00
microchip clk: microchip: mpfs: add reset controller 2022-09-14 10:55:17 +03:00
mscc net: dsa: felix: add support for changing DSA master 2022-09-20 10:32:36 +02:00
qcom mfd: qcom-spmi-pmic: read fab id on supported PMICs 2022-06-18 14:01:16 +01:00
rockchip soc: rockchip: power-domain: Manage resource conflicts with firmware 2022-05-09 03:36:52 +09:00
sa1100 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
sifive soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. 2022-10-13 11:06:51 -07:00
tegra soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 2022-09-15 12:41:36 +02:00