forked from Minki/linux
e4e2d7c388
Initial support for R-Car M3-W (r8a7796), including basic core clocks, and SCIF2 (console) and INTC-AP (GIC) module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
193 lines
6.2 KiB
C
193 lines
6.2 KiB
C
/*
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
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DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
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DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
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DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
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};
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static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
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DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
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DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
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};
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static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-AP (GIC) */
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
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* 14 13 19 17 (MHz)
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*-------------------------------------------------------------------
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* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
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* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
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* 0 0 1 0 Prohibited setting
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* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
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* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
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* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
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* 0 1 1 0 Prohibited setting
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* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
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* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
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* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
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* 1 0 1 0 Prohibited setting
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* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
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* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
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* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
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* 1 1 1 0 Prohibited setting
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* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
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(((md) & BIT(13)) >> 11) | \
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(((md) & BIT(19)) >> 18) | \
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(((md) & BIT(17)) >> 17))
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
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/* EXTAL div PLL1 mult PLL3 mult */
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{ 1, 192, 192, },
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{ 1, 192, 128, },
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{ 0, /* Prohibited setting */ },
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{ 1, 192, 192, },
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{ 1, 160, 160, },
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{ 1, 160, 106, },
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{ 0, /* Prohibited setting */ },
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{ 1, 160, 160, },
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{ 1, 128, 128, },
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{ 1, 128, 84, },
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{ 0, /* Prohibited setting */ },
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{ 1, 128, 128, },
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{ 2, 192, 192, },
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{ 2, 192, 128, },
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{ 0, /* Prohibited setting */ },
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{ 2, 192, 192, },
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};
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static int __init r8a7796_cpg_mssr_init(struct device *dev)
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{
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const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
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u32 cpg_mode = rcar_gen3_read_mode_pins();
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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if (!cpg_pll_config->extal_div) {
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dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
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return -EINVAL;
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}
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return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
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}
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const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r8a7796_core_clks,
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.num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r8a7796_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
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.num_hw_mod_clks = 12 * 32,
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/* Critical Module Clocks */
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.crit_mod_clks = r8a7796_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
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/* Callbacks */
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.init = r8a7796_cpg_mssr_init,
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.cpg_clk_register = rcar_gen3_cpg_clk_register,
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};
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