Yoshihiro Shimoda e0cb1b8416 clk: renesas: r8a7795: Fix SD clocks ... According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e539 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2016-08-11 17:47:56 -07:00
..
clk-div6.c
clk-div6.h	clk: renesas: div6: use RENESAS for #define	2016-03-15 18:13:02 -07:00
clk-emev2.c
clk-mstp.c	clk: renesas: mstp: Use always-on governor for Clock Domain	2016-04-28 10:32:51 +02:00
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rcar-gen2.c
clk-rz.c
clk-sh73a0.c
Kconfig	clk: renesas: Add R8A7792 support	2016-06-21 09:19:41 +02:00
Makefile	clk: renesas: Add R8A7792 support	2016-06-21 09:19:41 +02:00
r8a7795-cpg-mssr.c	clk: renesas: r8a7795: Fix SD clocks	2016-08-11 17:47:56 -07:00
r8a7796-cpg-mssr.c	clk: renesas: cpg-mssr: Add support for R-Car M3-W	2016-06-06 11:58:35 +02:00
rcar-gen3-cpg.c	clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code	2016-06-06 11:58:31 +02:00
rcar-gen3-cpg.h	clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code	2016-06-06 11:58:31 +02:00
renesas-cpg-mssr.c	clk: renesas: cpg-mssr: Add support for R-Car M3-W	2016-06-06 11:58:35 +02:00
renesas-cpg-mssr.h	clk: renesas: cpg-mssr: Add support for R-Car M3-W	2016-06-06 11:58:35 +02:00