Eric Bernstein 0b126112e9 drm/amd/display: DP YCbCr 4:2:0 support ... Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0 and BT2020 cases. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-06-15 12:20:27 -05:00
..
amdgpu_dm	drm/amd/display: Fix stale buffer object (bo) use	2018-06-13 13:45:23 -05:00
dc	drm/amd/display: DP YCbCr 4:2:0 support	2018-06-15 12:20:27 -05:00
include	drm/amd/display: Prefix TIMING_STANDARD entries with DC_	2018-06-15 12:20:27 -05:00
modules	drm/amd/display: HLG support	2018-06-15 12:20:26 -05:00
Kconfig	drm/amdgpu/display: remove VEGA20 config option	2018-05-18 16:08:18 -05:00
Makefile	drm/amd: Remove inclusion of non-existing include directories	2018-02-26 23:09:38 -05:00
TODO	drm/amd/display: Add TODO item to remove vector.c	2017-12-14 11:01:13 -05:00