do have a couple core changes in here as well.
Core:
- CLK_IS_CRITICAL support has been added. This should allow drivers
to properly express that a certain clk should stay on even if
their prepare/enable count drops to 0 (and in turn the parents of
these clks should stay enabled).
- A clk registration API has been added, clk_hw_register(), and
an OF clk provider API has been added, of_clk_add_hw_provider().
These APIs have been put in place to further split clk providers
from clk consumers, with the goal being to have clk providers
never deal with struct clk pointers at all. Conversion of provider
drivers is on going. clkdev has also gained support for registering
clk_hw pointers directly so we can convert drivers that don't use
devicetree.
New Drivers:
- Marvell ap806 and cp110 system controllers (with clks inside!)
- Hisilicon Hi3519 clock and reset controller
- Axis ARTPEC-6 clock controllers
- Oxford Semiconductor OXNAS clock controllers
- AXS10X I2S PLL
- Rockchip RK3399 clock and reset controller
Updates:
- MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x
SoCs, and some more clk ID exporting for bus frequency scaling
- Proper BCM2835 PCM clk support and various other clks
- i.MX clk updates for i.MX6SX, i.MX7, and VF610
- Renesas updates for R-Car H3
- Tegra210 got updates for DisplayPort and HDMI 2.0
- Rockchip driver refactorings and fixes due to adding RK3399 support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJXP7QdAAoJEK0CiJfG5JUl/Q8P/i93QXTom/VbwDHZ4DDZr0Hc
69oCRVTDTArGLa4YrGMxu3crNWf8/ORwsZVG93PD6bkkrWo9qH52KFsI22MdZcta
HlApsFjI503C7qDw6V8UVz7mUJVfarCxKNSd1WBPCVCNExarIrRRymC3NXT6ZrUP
D59E53d4G+I6OUuybsp4gtA7aEoYebAE7BInPDDihIk7Lall5mLYbfJUumpHlmSd
wqqPad5OYoC1nkrYhIGficK9Bizy3eyK829EoqpQpE4djkNhEwKd/AwSJZ6i1pdC
obt8vQyPRK0ByND2I+3XPqZ7bFb9IKu5WIAkYzG8QskFyIqiFtOkFgEP360ojlGT
D8sZY7RBmIM4Tu5RgeoN94wML4f/zYOm6YzVUVjWdVPGoxuy4QhQsvS5Id70ifNU
pSYf1KG0Gq0wvptth02zaDE9r1lDMOCHsOPIbVMqHRxRj8shUyjroTEzdtdyS6SE
FsYmGdrq4YctXyP4E8efLzFMjN7qZyKgnAoGfROsPRb6NE3DSFs5PcxQldOcoBPv
+NstBGUlJ4Xzwd1BdxKWJq8aIsG/CLqTec63OYSYM0bfUSWXKOgemvBV8MJrDP1D
rFabdJVHhUZOy5UgxOdfmy1XWp/SWup8OUnpEJp84RywGP6UMM0s1RtWruMJ776J
tBzVIIYCJrAWFia0Djlr
=aEzb
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"It's the usual big pile of driver updates and additions, but we do
have a couple core changes in here as well.
Core:
- CLK_IS_CRITICAL support has been added. This should allow drivers
to properly express that a certain clk should stay on even if their
prepare/enable count drops to 0 (and in turn the parents of these
clks should stay enabled).
- A clk registration API has been added, clk_hw_register(), and an OF
clk provider API has been added, of_clk_add_hw_provider(). These
APIs have been put in place to further split clk providers from clk
consumers, with the goal being to have clk providers never deal
with struct clk pointers at all. Conversion of provider drivers is
on going. clkdev has also gained support for registering clk_hw
pointers directly so we can convert drivers that don't use
devicetree.
New Drivers:
- Marvell ap806 and cp110 system controllers (with clks inside!)
- Hisilicon Hi3519 clock and reset controller
- Axis ARTPEC-6 clock controllers
- Oxford Semiconductor OXNAS clock controllers
- AXS10X I2S PLL
- Rockchip RK3399 clock and reset controller
Updates:
- MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
542x SoCs, and some more clk ID exporting for bus frequency scaling
- Proper BCM2835 PCM clk support and various other clks
- i.MX clk updates for i.MX6SX, i.MX7, and VF610
- Renesas updates for R-Car H3
- Tegra210 got updates for DisplayPort and HDMI 2.0
- Rockchip driver refactorings and fixes due to adding RK3399 support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
clk: fix critical clock locking
clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
clk: ingenic: Allow divider value to be divided
clk: sunxi: Add display and TCON0 clocks driver
clk: rockchip: drop old_rate calculation on pll rate changes
clk: rockchip: simplify GRF handling in pll clocks
clk: rockchip: lookup General Register Files in rockchip_clk_init
clk: rockchip: fix the rk3399 sdmmc sample / drv name
clk: mvebu: new driver for Armada CP110 system controller
dt-bindings: arm: add DT binding for Marvell CP110 system controller
clk: mvebu: new driver for Armada AP806 system controller
clk: hisilicon: add CRG driver for hi3519 soc
clk: hisilicon: export some hisilicon APIs to modules
reset: hisilicon: add reset controller driver for hisilicon SOCs
clk: bcm/kona: Do not use sizeof on pointer type
clk: qcom: msm8916: Fix crypto clock flags
clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
clk/axs10x: Add I2S PLL clock driver
clk: imx7d: fix ahb clock mux 1
clk: fix comment of devm_clk_hw_register()
...
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These warnings
are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXP3OZAAoJEPr7XbWNvGHDEUAQAJLbR9Js7RENPGX/u0NSJNaJ
yQhyNVsz/BkAWFfWT6YEfyNnDY0UcRs2N9RHb+z65TsX1jvJJxLRDLRfz+rExfiZ
cA1RJaF77kPOdA0eZapJIzPvAf97Zik+nzKLsqUPUSYaIzghV5rN6aR2AjXN5AYv
TMQP41NwNQkxfO5I+NOssEB8IBH+DlAzg0LYXw8wNsAJc8o+DgEQjU8cxCqR0NgE
SbpbJNF8tRXEJckZRC+Q7Gyn2J7VglmM/5VTFbBBwgIly2lcLADPVuX/Z6hZE3OH
K7mhNWBu61vI5lU6u7q64ePeb63j+Ut/RR0tTPgjsLg0Qg0ue+6iZ66S9ZHEicbU
wT4A/hjSImvZoQGGMrtUF5HGcaoMHGLGFgFc/Ouox8OQflntQBzuEx/gOQpPXcIT
vdwITNW8/OGV3rgtmRO9mbdSZiAHPsydoTkIl+Ucod3nTrlEEOwgQARYO+2CfSRj
sknndj26Kf+0n0tSv2d4JAEdEozp2ZPyfiAfpPXW74jOmOxeswUb3Kxx8YMwhCEl
+s96rm1vtpNmJzXtuPV3eB0TydWMQ/3NXN6XOS7qEN/5y1AbQqKEoIyJOziBQMxe
c9Eh/YSjsm4uw3Q0wHOI3s4hTwWfuBmwpIsANJVKrRbftPF58bMUBYU/44ReTtA8
iMsrqJpnSCcAyS8doWRY
=s+gW
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These
warnings are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
* tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (52 commits)
devicetree: Add Creative Technology vendor id
gpio: dt-bindings: add ibm,ppc4xx-gpio binding
of/unittest: Remove unnecessary module.h header inclusion
drivers/of: Fix build warning in populate_node()
drivers/of: Fix depth when unflattening devicetree
of: dynamic: changeset prop-update revert fix
drivers/of: Export of_detach_node()
drivers/of: Return allocated memory from of_fdt_unflatten_tree()
drivers/of: Specify parent node in of_fdt_unflatten_tree()
drivers/of: Rename unflatten_dt_node()
drivers/of: Avoid recursively calling unflatten_dt_node()
drivers/of: Split unflatten_dt_node()
of: include errno.h in of_graph.h
of: document refcount incrementation of of_get_cpu_node()
Documentation: dt: soc: fix spelling mistakes
Documentation: dt: power: fix spelling mistake
Documentation: dt: pinctrl: fix spelling mistake
Documentation: dt: opp: fix spelling mistake
Documentation: dt: net: fix spelling mistakes
Documentation: dt: mtd: fix spelling mistake
...
Pull some non-critical i.MX clk fixes from Shawn Guo:
* Fix the commit 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
which messed up the clock enumeration when adding new clock.
* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx35: restore existing used clock enumeration
clk: imx6q: fix typo in CAN clock definition
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.
Add a driver to support both.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Silence variable sized array warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and
display-related clocks.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXI4/UAAoJEBx+YmzsjxAgJ9sP/iAKVRDJt/ng0Zw+niGC8EMZ
AdqXCSbRj7bwnIyT+0ETEFIhaUTXVEg0wIfEQxPKIMOatL51OlR0Iuwviji43IeF
oJUDQHSuKOZav7mlLKuEQJIOQBlqbMqjSecFyPN7yqRS9+qD+bDxWE54wXxapXPN
QT/RT7662cSUWzmeUFE5OcBd8AIHQp32ozeWFA7kezfExUqQXHopFi98e0erba+x
Z74cfC7aNOce3BcgpiyY0UdfHWIGZxkTEFp6KELX92gCrGVghQ+SjOTyp6FIcU/N
Y+3BEsjMEByRfhxokKdmReoOAHlHJOmPlERa7vUqsksbEHYtNbbQxRMag76R00hI
BdOASfvHcJVSeQQWKgOcdHoHCZcNubgDMjqv0aRY1ZX7MeVg1qxw+XEhsunUTNay
Ifjq2qRLY2dGOioUk9adCorr3Z+Of9uPjB1VTQSbrKgJLe7fMdXp8ww6iNxQZ9eo
x5JtjaJ2sREFQNGK8WzpImCJ5g6Oa0GQ7C4Lg/Y3obFRnsBiGDKLJDwmbHkhO/ZK
i8N7AXIum0k+Tad8ndLLTahKJ4iH46E2RKDbieCzRIW0oqnB+nAzsm4a2SG3AJFR
hB11sL3WCugDDJHCQvzCzdadHXSOYJC3g30r/WC7jr6ri0c7IHXQ0OHHhF1d36Ms
rzWKUbSyINwTXtjijfiS
=ttF/
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock driver updates from Maxime Ripard:
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and
display-related clocks.
* tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi: Let divs clocks read the base factor clock name from devicetree
clk: sunxi: Add TCON channel1 clock
clk: sunxi: Add PLL3 clock
dt-bindings: clk: sun5i: add DRAM gates compatible
clk: sunxi: Use resource_size
clk: sunxi: Add sun6i/8i display support
clk: sunxi: mod1 clock should modify it's parent
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.
It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).
Add a driver for the channel 1 clock.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the clock type which is used by the sun6i/8i families for video display.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
A new element got inserted into enum mx35_clks with commit 3713e3f5e9
("clk: imx35: define two clocks for rtc"). This insertion shifted most
nummerical clock assignments to a new nummerical value which in turn
rendered most hardcoded nummeric values in imx35.dtsi incorrect.
Restore the existing order by moving the newly introduced clock to the
end of the enum. Update the dts documentation accordingly.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Fixes: 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Added unit address to binding example]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add DT binding documentation for lpc1850-creg-clk driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull Allwinner clk updates from Maxime Ripard:
Allwinner clocks additions for 4.6
A bunch of things, mostly:
- Finally switched everything over to OF_CLK_DECLARE, which should remove
orphans clocks entirely
- Reworked the clk-factors to be able to add new parameters
- Improved the error reporting
- A bunch of new clocks for new SoCs.
* tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
clk: sunxi: Add apb0 gates for H3
clk: sunxi: Improve divs_clk error handling and reporting
clk: sunxi: improve divider_clk error handling and reporting
clk: sunxi: improve mux_clk error handling and reporting
clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
clk: sunxi: Remove clk_register_clkdev calls
clk: sunxi: Remove old probe and protection code
clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
clk: sunxi: Make clocks setup functions take const pointer
clk: sunxi: Make clocks setup functions return their clock
clk: sunxi: improve error reporting for the mux clock
clk: sunxi: don't mark sun6i_ar100_data __initconst
clk: sunxi: add bus gates for A83T
clk: sunxi: Add apb0 gates for A83T
clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
clk: sunxi: rewrite sun6i-ar100 using factors clk
clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
clk: sunxi: factors: Drop round_rate from clk ops
clk: sunxi: factors: Support custom formulas
clk: sunxi: factors: Consolidate get_factors parameters into a struct
...
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.
Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.
Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A83T has similar bus gates that of H3, including single gating register has
different clock parent.
As per H3 and A83T datasheet, usbhost is under AHB2.
However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits 29, 30, 31(ohci0,1,2) => AHB2 for H3.
until, this confusion is cleared keep it H3 way.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJWm9wLAAoJEPOmecmc0R2BfbUIAI7VaIzwhl4NkAO3x0P6emZT
B/2C4RuPLW9oBf/YGxG+HsxD2iLpDjAlZADlGBXsrdkfjFuN0iULc8COrFJEGv0F
HuFmxJz7IZCNS4BgXt+vk0yb43c1lLSMRSmTyWaY7izYUlQtcmDp/t7zTvwun9NM
N2U44zXFsEnTtsb3gV65PivrMBT/sNK9MyOIylh3Xjs/v+fTCtsHwPVckFwiIiPx
ER9ETDmeo/DEMtsutHTlCcujyvZXE3jsho0Ow7J/vuRJSbXkCW+Ki9CQZEvHGWXL
7ZaST8A8LEBjvslCh9IkirZ7qi20wwk/md3zAeoE0+eimEOEIqWYF8qwsWHiJjU=
=oT+p
-----END PGP SIGNATURE-----
Merge tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
Pull rockchip fixes from Heiko Stuebner:
Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.
* tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3368: fix some clock gates
clk: rockchip: rk3036: rename emac ext source clock
clk: rockchip: rk3036: fix the div offset for emac clock
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: fix the FLAGs for clock mux
The clock generator has two clock inputs that can be used as the reference
clock. Add support for switching between them at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds audio clock device tree binding documentation to an
existing Cygnus clock DT bindings document.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Lori Hikichi <lhikichi@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Update APM X-Gene clock binding documentation for SoC and
PCP PLL for v2 hardware.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As usual, the bulk of this release is again DT file contents.
There's a huge number of changes here, and it's challenging to give a crisp
overview of just what is in here. To start with:
New boards:
- TI-based DM3730 from LogicPD (Torpedo)
- Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
- Raspberry Pi 2 DT files
- Watchdog on Meson8b
- Veyron-mickey (ASUS Chromebit) DTS
- Rockchip rk3228 SoC and eval board
- Sigma Designs Tango4
Improvements:
- Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
- Misc new devices for Rockchip rk3036 and rk3288
- Allwinner updates for misc SoCs and systems
... and a _large_ number of other changes across the field. Devices
added to SoC DTSI and board DTS files for a number of SoC vendors, new
product boards on already-supported SoCs, cleanups and refactorings of
existing DTS/DTSI files and a bunch of other changes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWnr6fAAoJEIwa5zzehBx3p+gP+wYLUqXjCYgyu6oJPxJbWghj
gPc4QJmhVlAWTqvE7Ut7RumWzGa7nUEH2QF9tiCLbDAw8727HJXhRHknFwaCsX45
BsvFQaKY99ClfUhoSI9GRa8e2jEArjzEPqkynHW/8FM20qWaj/Z8DDfixG75gR8u
onrMw6kprNGwmyQwqu5zLDXhUBCQIs1xRRSabUjV1P5420dbBaGgtmQrdj7k+JDt
wo9SKiG6d9CSYil3r7BC+0JwzbKNBxRGs2vv1BJOfbZ3Lj+uC0vj1AxoF/p7dOHy
ohuvt7UwwtoUzzFMcMUo7E8qxl9u6bbnPDlUoRF7DVVi5SQoeZd8BOZXOdLRN2OQ
qtgsmziDxtvh7Ydj6i89D69x7+GurAFcP8Aturprc5Zd5lO70PAYBD379IhIZ8y1
MVJltIEeuUZo7BaVBCHWQY9jJRtI3bAU6JdFPrFROsuo810IYd72Wbb1ZCfF7SV7
nBRvV7e71VQxb48c3p8Et5FntHuXfUlhkMrQ7Cb+2ugB/diGgZB9NfrZbP3Azv7f
A5Ey9tNHaOCUxzYDCw80jTa7OwVWNJf2kOT1yikASk3vODKLv4E5YQ2DULnObWG7
iRmLYuuGka4sMs0ZjpV3kaqs+8rWu08x2rEr5X0wfU+DalIzUWA2oDKSgPLJoacV
gXKP039CIxQAiottcppA
=XDLa
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As usual, the bulk of this release is again DT file contents.
There's a huge number of changes here, and it's challenging to give a
crisp overview of just what is in here. To start with:
New boards:
- TI-based DM3730 from LogicPD (Torpedo)
- Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
- Raspberry Pi 2 DT files
- Watchdog on Meson8b
- Veyron-mickey (ASUS Chromebit) DTS
- Rockchip rk3228 SoC and eval board
- Sigma Designs Tango4
Improvements:
- Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
- Misc new devices for Rockchip rk3036 and rk3288
- Allwinner updates for misc SoCs and systems
... and a _large_ number of other changes across the field. Devices
added to SoC DTSI and board DTS files for a number of SoC vendors, new
product boards on already-supported SoCs, cleanups and refactorings of
existing DTS/DTSI files and a bunch of other changes"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits)
ARM: dts: compulab: add new board description
ARM: versatile: add the syscon LEDs to the DT
dts: vt8500: Fix errors in SDHC node for WM8505
ARM: dts: imx6q: clean up unused ipu2grp
ARM: dts: silk: Add compatible property to "partitions" node
ARM: dts: gose: Add compatible property to "partitions" node
ARM: dts: porter: Add compatible property to "partitions" node
ARM: dts: koelsch: Add compatible property to "partitions" node
ARM: dts: lager: Add compatible property to "partitions" node
ARM: dts: bockw: Add compatible property to "partitions" node
ARM: dts: meson8b: Add watchdog node
Documentation: watchdog: Add new bindings for meson8b
ARM: meson: Add status LED for Odroid-C1
ARM: dts: uniphier: fix a typo in comment block
ARM: bcm2835: Add the auxiliary clocks to the device tree.
ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B
ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT.
ARM: bcm2835: Split the DT for peripherals from the DT for the CPU
ARM: realview: set up cache correctly on the PB11MPCore
ARM: dts: Unify G2D device node with other devices on exynos4
...
Drop the bogus "sh73a0-" part (accidentally copied from shmobile?) from
the compatible value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There is only support rmii in the RK3036, so we should use the correct
ext clock name as described in the TRM.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[update dt-binding document as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
bulk of the changes are to clk controller drivers, though some
improvements to the core and some re-usable blocks/templates also
received some love. In this past cycle the clk maintainers developed a
good workflow for handling the common case of patch submissions
containing a new drivers, new shared Device Tree header and a new Device
Tree binding description. This requires coordination with the Device
Tree maintainers and with the architecture maintainers (typically the
arm-soc tree in our case). This explains the increase in changes to
include/dt-bindings/... and to
Documentation/devicetree/bindings/clock/... coming from the clk tree.
The same commits can be expected to come through those trees on
occasion, through the use of shared, immutable branches.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJWmVD1AAoJEKI6nJvDJaTUWqAQAJRqH+iKSnLyuVek6USYPXdp
ZOW1JHIySCUF/ci3fvv9vbIuW/w4Uc9FdRdAfIIaWO32bpk4ljtEogVasvavL/54
geN+0YERZpth+PL/wk+g+Dons/8BgN9AL+0ToaVVh2MsRE903jWpe+l0qWCl+SUn
DQF+yB9F4QcVT7gb+KI0B6hr6lv5Mu/t9Ffq3DrK2UG71IEbrv953pVo19foZqbf
FgMgduERMHvaM/R6p5xfXxIESbjE+QNMnykEo6bWcHF2wfQrIiYlW1khtnsigNus
kze2mYWjG77KGkrOex5kwjuBDPfiaGAstk3jcRCCMB7nRmuFcJgryF8003CD3QvW
+cY+ZBSkyXXtL/nrkefebAplQjsvum7dJ+W6hxA32B772jFL8s8ee5rGda0ibw8N
nFQRopVcNPoR52tjmSEOxm7Z9vqoDj5qManDdZe62kr6bCFId97E6SzeGgeyDuBQ
V7tkss9klHMhx29V37wkyl+A/pWXO+CsGzHLEivH8/L1CysMK1WGhyHJJ2/JTDTR
n3z1EYdg67PbHpfhboscuLP+sHcrAefOCe2la4wKxwqd4DGw6J8RhhVZml6XnfQ3
I4yLri8Pguol49G1ac1U87ylebKsXhWR5CRHVas1BFHrt0FGULHnl0ZOLzOu4GRZ
h8/nd9ZODLFhB1w7fL1B
=nkGr
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk framework updates from Michael Turquette:
"The clk framework and driver changes for 4.5 look pretty typical. The
bulk of the changes are to clk controller drivers, though some
improvements to the core and some re-usable blocks/templates also
received some love.
In this past cycle the clk maintainers developed a good workflow for
handling the common case of patch submissions containing a new
drivers, new shared Device Tree header and a new Device Tree binding
description. This requires coordination with the Device Tree
maintainers and with the architecture maintainers (typically the
arm-soc tree in our case).
This explains the increase in changes to include/dt-bindings/... and
to Documentation/devicetree/bindings/clock/... coming from the clk
tree. The same commits can be expected to come through those trees on
occasion, through the use of shared, immutable branches"
* tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: remove duplicated COMMON_CLK_NXP record from clk/Kconfig
clk: fix clk-gpio.c with optional clock= DT property
clk: rockchip: fix section mismatches with new child-clocks
clk: gpio: handle error codes for of_clk_get_parent_count()
clk: gpio: fix memory leak
clk: shmobile: r8a7795: Add SATA0 clock
clk: bcm2835: Add PWM clock support
clk: bcm2835: Support for clock parent selection
clk: bcm2835: add a round up ability to the clock divisor
clk: lpc32xx: add common clock framework driver
clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol
dt-bindings: clock: add NXP LPC32xx clock list for consumers
dt-bindings: clock: add description of LPC32xx USB clock controller
dt-bindings: clock: add description of LPC32xx clock controller
clk: rockchip: rk3036: include downstream muxes into fractional dividers
clk: add flag for clocks that need to be enabled on rate changes
clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
clk: rockchip: include downstream muxes into fractional dividers
clk: rockchip: handle mux dependency of fractional dividers
clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
...
Bindings for Samsung S2M and S5M family PMICs are in mess. They are
spread over different files and subdirectories in a non-consistent way.
The devices and respective drivers for them share a lot in common so
everything could be organized in a more readable way.
Reorganize the S2MPS11/13/14/15 Device Tree bindings to match the
drivers for this family of devices:
- move mfd/s2mps11.txt to mfd/samsung,sec-core.txt for the main MFD
driver (common for entire family),
- split clock block to clock/samsung,s2mps11.txt,
- split regulator block to regulator/samsung,s2mps11.txt.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJWcq0qAAoJEN0jrNd/PrOhxXIP/Rs/Iw27BVfk/ZYA+9SaYlNz
vxqzGqWincnlaArLuhAnUHciAv5kl3HnHEuOyAgFevX/KrnmAb5JMXuw2FaSmzPc
hjI5QqeieEHqp0wFSms/+abTiLX5t36bsY91QM8LfsdDOotrYGwEJcqDVEZkvMF2
j3U4RuXEqt/C0r436lPcxf+flvy70K1cQkywsKupcS4YGl0QiQVeY80tHmIIyrkA
2KLkxH5zgs/6xlcGblqzkFmrQntp5XJVgdlg1e2SZ5MOOme9fQCU0F3VueOX+WZH
FL4C05eaXCaga398Z/UgJru1X8HWUKzrGBX6XXktxeTjt8ruKD8PEjX7SVPYMRI9
Kzb3NE5qC0LEwe/BAX/4scZ6fZFyk+zfiC566YA3rcM1sg5mm4k8PCH3x2ktxXI1
SZYmIrm+9hXXWfvXlKysaIsmGL0hlsRlu6m6g2OEYTUABDMBLnMsTbeC6Li4Gh0Q
kXISNZpMhRaiB1hba3z2J/sVuMQcR33e86IaAX7WFY4ZRTNKfD0oB2zN5lZjPO6o
U9ATB5ApPWn3t0JR88jaApPVELVb5q6ufra2zPesnS25CfS+zSXbskgnZe9UkPAs
XVUprlmsNm+vZbZJpf3eNtW2IS0c0vCAYkafY3KjWcKVKvgKw5Zu8Kdo1TAJTHbP
+xfWr3/iiwN5NNsYZbiH
=/f1y
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.5-rc1
This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
NXP LPC32xx USB controller has a subdevice, which controls USB AHB
slave, USB OTG, USB OHCI, USB device and I2C controller to USB phy
clocks, this change adds description of the clock controller, for more
details reference LPC32xx User's Manual, namely USB control, OTG clock
control and OTG clock status registers.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
of system control block (SCB). CPC is supplied by two external
oscillators and it manages core and most of peripheral
clocks, the change adds description of DT bindings for clock
controller found on LPC32xx SoC series.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Clock patches for the Allwinner SoCs:
- H3 clocks
- A10/A20 Video Engine clocks
- DRAM gates
- A80 special CPU clock
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWcyKFAAoJEBx+YmzsjxAgtNMP/jJWzfh8bLB+eCZHGtBm/Y86
em0DaAFWoAYOo0iFGRNkiJ+Gk5lOFx/qLjMbHitfEk00lNs9L2Goyzhko1WnaLQ6
ZmJK1X3bcd5Uyqa3O8RP3zu0NUDin4sU4ZhKT8PuSkPEO69wSlgn+4R3e46jlRVg
+1dbeEs68N10PjIBPqoCDYuP3YJW+nbdJQ03M4M9W6xNVgxtz/FVv1i3W61m3+r2
LInUfr4A/+Mr3hNlGol4PEq8HP4xdfXRnrnSPNKJfysxc+9e2al6hmfiiBlSyhV2
Z6HPG2qaxWMGCBG/q0SOh0I1vL8CgWbw0E04Wu5hzSBBaaS+KIEU6KqMQKFLyw5C
U5V4z0g2ePs8SZD3SB1taB2y3dVtCwtOWvo/teAOKc7zXe/3wPRAWyxg4N5IGX/C
bwHQGrDKuwsXVySAXqPXEojwTToF/TxqsS1RpunjLA2JIb1dvREUP0MMPXgPZJKN
yiZLfeWw4SDonSPagSy/AQuEjih5ekZmT2aIOU4oCAqjpre6gQaolQn1xriL+ACf
qdT4Hcg2hzlkjPB0N9izI7Krcef4oZpzZqls2/M9CnmTeMY4l2z9lZylqto4HnLF
VT3duWXlmh8g9YGiWpMWwtcl0kXxP2mYM959k9KFrtvX7lhN4T2hmJwRnnCRCKre
Zpt/9dotvmyM5Dno0Pee
=Tahe
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clocks-for-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clocks changes for 4.5
Clock patches for the Allwinner SoCs:
- H3 clocks
- A10/A20 Video Engine clocks
- DRAM gates
- A80 special CPU clock
