Commit Graph

180696 Commits

Author SHA1 Message Date
Vimarsh Zutshi
e8d373779e OMAP3: clock: add capability to change rate of dpll4_m5_ck_3630
Add necessary clk_sel definitions to clock framework to allow changing
dpll4_m5_ck_3630 rate. This is used by the ISP driver.

Signed-off-by: Vimarsh Zutshi <vimarsh.zutshi@nokia.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:29:43 -07:00
Paul Walmsley
53c92d8f20 OMAP4 clock: drop the ALWAYS_ENABLED clock flag
Get rid of the ALWAYS_ENABLED clock flag - it doesn't actually do anything.
(The OMAP4 clock autogeneration scripts have been updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
2010-02-24 12:29:43 -07:00
Paul Walmsley
51c1954162 OMAP clock: drop RATE_FIXED clock flag
The RATE_FIXED clock flag is pointless.  In the OMAP1 clock code, it
simply causes the omap1_clk_round_rate() function to return the
current rate of the clock.  omap1_clk_round_rate(), however, should
never be called for a fixed-rate clock, since none of these clocks
have a .round_rate function pointer set in their struct clk records.
Similarly, in the OMAP2+ clock code, the RATE_FIXED flag just causes
the clock code to emit a warning if the OMAP clock maintainer was
foolish enough to add a .round_rate function pointer to a fixed-rate
clock.  "Doctor, it hurts when I pretend that a fixed-rate clock is
rate-changeable."  "Then don't pretend that a fixed-rate clock is
rate-changeable."  It has no functional value.  This patch drops the
RATE_FIXED clock flag, removing it from all clocks that are so marked.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:29:43 -07:00
Paul Walmsley
8c34974ab0 OMAP2 clock: drop DELAYED_APP clock flag
All of the clocks that are marked with DELAYED_APP are changed as part
of the virt_prcm_set OPP virtual clock.  On 24xx, these clocks all
need to be changed as part of a group to keep the clock tree
functional - hence the need for the VALID_CONFIG bit, which is not
present on later OMAPs.  These clocks should not be rate-changed
independently.  So prevent these clocks from being changed
independently by dropping their .round_rate and .set_rate function
pointers.  It then turns out that the DELAYED_APP clock flag is no
longer useful, so drop it and the associated code and renumber the
clock flags.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:29:42 -07:00
Paul Walmsley
5173804fbb OMAP2430 clock: make func_96m_ck parent-selectable
func_96m_ck was incorrectly marked as being rate-selectable, when in
fact it is only parent-selectable.  Remove the .set_rate and .round_rate
function pointers for this clk.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:29:42 -07:00
Paul Walmsley
81b34fbecb OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c.  2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both.  We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures.  The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.

This approach does have some nice benefits beyond multi-OMAP 2 kernel
support.  The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in.  (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.)  It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.

This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.

While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.

Thanks to Tony for some good discussions about how to approach this
problem.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:29:42 -07:00
Paul Walmsley
657ebfadc1 OMAP3/4 clock: split into per-chip family files
clock34xx_data.c now contains data for the OMAP34xx family, the
OMAP36xx family, and the OMAP3517 family, so rename it to
clock3xxx_data.c.  Rename clock34xx.c to clock3xxx.c, and move the
chip family-specific clock functions to clock34xx.c, clock36xx.c, or
clock3517.c, as appropriate.  So now "clock3xxx.*" refers to the OMAP3
superset.

The main goal here is to prepare to compile chip family-specific clock
functions only for kernel builds that target that chip family.  To get to
that point, we also need to add CONFIG_SOC_* options for those other
chip families; that will be done in future patches, planned for 2.6.35.

OMAP4 is also affected by this.  It duplicated the OMAP3 non-CORE DPLL
clkops structure.  The OMAP4 variant of this clkops structure has been
removed, and since there was nothing else currently in clock44xx.c, it
too has been removed -- it can always be added back later when there
is some content for it.  (The OMAP4 clock autogeneration scripts have been
updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
2010-02-24 12:16:15 -07:00
Paul Walmsley
b92c170d01 OMAP clock: drop .id field; ensure each clock has a unique name
After the clkdev conversion, the struct clk.id field became
superfluous, so, drop it.  Bring the clock names closer to the TRMs
and ensure they are unique for debugfs.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:16:13 -07:00
Paul Walmsley
f71eddb158 OMAP clock: compress clock flags down to a u8
There are now only eight OMAP clock flags, so renumber the flags to
fit in a u8 and shrink the size of struct clk.flags from a u32 to a
u8.  The intention is to save memory.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:15:06 -07:00
Paul Walmsley
1a3377176b OMAP2 clock: drop CONFIG_PARTICIPANT clock flag
It turns out that the only purpose of the CONFIG_PARTICIPANT clock
flag is to prevent omap2_clk_set_rate() and omap2_clk_set_parent()
from being executed on clocks with that flag set.  The rate-changing
component can be more directly accomplished by dropping the .set_rate
and .round_rate function pointers from those CONFIG_PARTICIPANT struct
clks.  As far as the parent-changing component is concerned, it turns
out that none of the CONFIG_PARTICIPANT clocks have multiple parent
choices, so all that is necessary is for omap2_clk_set_parent() to
bail out early if the new parent is equal to the old parent.
Implement this change and get rid of the flag, which has always had a
confusing name (it appears to be a Kconfig option, falsely).

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:15:04 -07:00
Paul Walmsley
17d092733d OMAP2xxx clock: drop DELAYED_APP flag from non-clksel clocks
The DELAYED_APP flag is effective only with clksel clocks, so drop it from
clocks that are not rate-changeable or that use non-clksel rate changing code
(e.g., virt_prcm_set).

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:15:04 -07:00
Paul Walmsley
94297784ee OMAP2xxx clock: GFX functional clock rates are not independently changeable
According to the OMAP242x TRM Rev X Figure 5-15 "Clock Output Control
- Functional Clocks 2", the GFX functional clocks should be marked
both DELAYED_APP and CONFIG_PARTICIPANT, meaning that their rates must
be reprogrammed as part of a larger OPP set change.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-24 12:15:04 -07:00
Paul Walmsley
c78a05e8e4 OMAP4 clock: drop the CLOCK_IN_OMAP4430 clock flag
The CLOCK_IN_OMAP4430 clock flag is not currently needed in the OMAP4
ES1 clock tree, and platform discrimination via clock flags is
deprecated in favor of the clkdev mechanism, so, drop it.  (The OMAP4
clock tree autogeneration script has been updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-24 12:15:04 -07:00
Paul Walmsley
93340a2294 OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be.  See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL".  Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode.  Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.

Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_.  (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.)  This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".

While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed.  The OMAP4 clock autogenerator script has been updated
accordingly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-24 12:15:03 -07:00
Vishwanath BS
7356f0b26b OMAP3 clock: add support for 192Mhz DPLL4M2 output
In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at
192). This patch has changes to support this feature. 96MHz clock is
generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's
functional clock. In summary changes done are:
1. Added a feature called omap3_has_192mhz_clk and enabled for 3630
2. Added a new clock node called omap_192m_alwon_ck
3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck

Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: fixed whitespace]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:15:03 -07:00
Vishwanath BS
678bc9a2ea OMAP3 clock: Introduce 3630 DPLL4 HSDivider changes
Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit
in 3630. This patch has changes to accommodate this in CM dynamically
based on chip version.
Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and
M6 and value of these nodes are used if cpu type is 3630.

Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
[paul@pwsan.com: updated to apply on 2.6.34 queue; comments added]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:15:03 -07:00
Richard Woodruff
358965d7ba OMAP3 clock: introduce DPLL4 Jtype
DPLL4 for 3630 introduces a changed block called j type dpll, requiring
special divisor bits and additional reg fields. To allow for silicons to
use this, this is introduced as a flag and is enabled for 3630 silicon.
OMAP4 also has j type dpll for usb.

Tested with 3630 ZOOM3 and OMAP3430 ZOOM2

Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: added some comments; updated copyrights and credits; fixed
 some style issues]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:15:02 -07:00
Abhijit Pagare
91808a81fe ARM: OMAP4 clock domain: Add check for avoiding dependency related update.
A check is added for avoiding the sleep/wakeup dependency updates
for OMAP4 as the structures for the dependencies are currently absent.

Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
[paul@pwsan.com: added warnings, explanatory comment, copyright update]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:14:59 -07:00
Mike Turquette
a7e069fc5a OMAP3630: Clock: Workaround for DPLL HS divider limitation
This patch implements a workaround for the DPLL HS divider limitation
in OMAP3630 as given by Errata ID: i556.

Errata:
When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx).
The reset value gets loaded instead of the previous value.
The following HSDIVIDERs exhibit above behavior:
. DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits)
. DPLL3 : M3 (CM_CLKEN_PLL[12] register bit).

Work Around:
It is mandatory to apply the following sequence to ensure the write
value will
be loaded in DPLL HSDIVIDER FSM:
The global sequence when using PWRDN bit is the following:
. Disable Mx HSDIVIDER clock output related functional clock enable bits
        (in CM_FCLKEN_xxx / CM_ICLKEN_xxx)
. Enable PWRDN bit of HSDIVIDER
. Disable PWRDN bit of HSDIVIDER
. Read current HSDIVIDER register value
. Write different value in HSDIVIDER register
. Write expected value in HSDIVIDER register
. Enable Mx HSDIVIDER clock output related functional clocks
        (CM_FCLKEN_xxx / CM_ICLKEN_xxx)

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com>
[paul@pwsan.com: updated patch to apply; made workaround function static;
 marked as being 36xx-specific]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:06:00 -07:00
Thara Gopinath
c23a97d377 OMAP: HWMOD: Add support for early device register into omap device layer
This patch adds support in omap device layer to register devices
as early platform devices. Certain devices needed during system boot up
like timers, gpio etc can be registered as early devices. This will
allow for them to be probed very early on during system boot up.
This patch adds a parameter is_early_device in omap_device_build.
Depending on this parameter a call to early_platform_add_devices
or platform_register_device is made.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:58 -07:00
Thara Gopinath
358f0e630d OMAP3: hwmod: support to specify the offset position of various SYSCONFIG register bits.
In OMAP3 Some modules like Smartreflex do not have the regular sysconfig
register.Instead clockactivity bits are part of another register at a
different bit position than the usual bit positions 8 and 9.

In OMAP4, a new scheme is available  due to the new protocol
between the PRCM and the IPs. Depending of the scheme, the SYSCONFIG
bitfields position will be different.
The IP_REVISION register should be at offset 0x00.
It should contain a SCHEME field. From this we can determine whether
the IP follows legacy scheme or the new scheme.

31:30 SCHEME  Used to distinguish between old scheme and current.
 Read 0x0:  Legacy protocol.
 Read 0x1:  New PRCM protocol defined for new OMAP4 IPs

For legacy IP
 13:12 MIDLEMODE
 11:8  CLOCKACTIVITY
 6     EMUSOFT
 5     EMUFREE
 4:3   SIDLEMODE
 2     ENAWAKEUP
 1     SOFTRESET
 0     AUTOIDLE

For new OMAP4 IP's, the bit position in SYSCONFIG is (for simple target):
 5:4   STANDBYMODE (Ex MIDLEMODE)
 3:2   IDLEMODE (Ex SIDLEMODE)
 1     FREEEMU (Ex EMUFREE)
 0     SOFTRESET

Unfortunately In OMAP4 also some IPs will not follow any of these
two schemes. This is the case at least for McASP, SmartReflex
and some security IPs.

This patch introduces a new field sysc_fields in omap_hwmod_sysconfig which
can be used by the hwmod structures to specify the offsets for the
sysconfig register of the IP.Also two static structures
omap_hwmod_sysc_type1 and omap_hwmod_sysc_type2 are defined
which can be used directly to populate the sysc_fields if the IP follows
legacy or new OMAP4 scheme. If the IP follows none of these two schemes
a new omap_hwmod_sysc_fields structure has to be defined and
passed as part of omap_hwmod_sysconfig.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:58 -07:00
Vishwanath BS
5eb75f5578 OMAP3 clock: Remove FreqSel for 3630
DPLL_FREQSEL field in CLKEN_PLL register is no longer valid for
OMAP3630. So remove references to that.

Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
[paul@pwsan.com: added comment fix from Sergei Shtylyov]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:57 -07:00
Kevin Hilman
0cc9314eaf OMAP2/3: PRCM: fix misc. compiler warnings
- missing return in omap_prcm_get_reset_sources()
- potential use of uninitialized variable in omap_prcm_arch_reset()

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:56 -07:00
Sanjeev Premi
a51ba28407 OMAP3 clock: Check return values for clk_get()
This patch checks if clk_get() returned success for
the clocks used in function omap2_clk_arch_init().

This version incorporates review comments from
Kevin Hilman and Paul Walmsley.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:56 -07:00
Ranjith Lohithakshan
3cc4a2fc2e AM35xx: Add clock support for new modules on AM35xx
This patch adds clock support for the following AM35xx modules
	- Ethernet MAC
	- CAN Controller (HECC)
	- New MUSB OTG Controller with integrated Phy
	- Video Processing Front End (VPFE)
	- Additional UART (UART4)

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:55 -07:00
Ranjith Lohithakshan
419cc97d36 OMAP2/3 clock: Extend find_idlest() to pass back idle state value
Current implementation defines clock idle state indicators based on the
cpu information (cpu_is_omap24xx() or cpu_is_omap34xx()) in a system wide
manner. This patch extends the find_idlest() function in clkops to pass
back the idle state indicator for that clock, thus allowing idle state
indicators to be defined on a per clock basis if required.

This is specifically needed on AM35xx devices as the new IPSS clocks
indicates the idle status (0 is idle, 1 is ready) in a way just
opposite to how its handled in OMAP3 (0 is ready, 1 is idle).

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
[paul@pwsan.com: updated to apply after commit 98c45457 et seq.]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:54 -07:00
Thara Gopinath
cde08f81b1 OMAP3 PM: Adding counters for power domain logic off and mem off during retention.
This patch adds counters to keep track of whether the powerdomain
logic or software controllable memory banks are turned off when
the power domain enters retention. During power domain retention
if logic gets turned off, the scenario is known as Open Switch Retention.
Also during retention s/w controllable memory banks of a power
domain can be chosen to be kept in retention or off.

This patch adds one counter per powerdomain to track the power domain
logic state during retention. Number of memory bank state counters
added depends on the number of software controllable memory banks
of the powerdomain. To view these counters do
	cat ../debug/pm_debug/count

Signed-off-by: Thara Gopinath <thara@ti.com>
[paul@pwsan.com: conditional expressions simplified; counter increment
 code moved to its own function]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:50 -07:00
Thara Gopinath
4133a44e28 OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structure
This patch adds the flag .pwrsts_logic_ret info for the core power domain
in the associated powerdomain structure. This flag specifies the states
core domain logic can hit in event of the domain entering retention.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:50 -07:00
Thara Gopinath
1e3d0d2ba9 OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem state
This patch adds APIs pwrdm_read_logic_retst and
pwrdm_read_mem_retst for reading the next programmed
logic and memory state a powerdomain is to hit in event
of the next power domain state being retention.
These are needed for OSWR support.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:49 -07:00
Tero Kristo
b024b542c3 OMAP3: Clock: Added IDLEST definitions for SGX
Added definitions for OMAP3430ES2_ST_SGX_SHIFT and OMAP3430ES2_ST_SGX_MASK
as these were missing.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:48 -07:00
Kevin Hilman
dfa6d6f892 OMAP3: clock: use std _MASK suffix for CM_FCLKEN_IVA2 defines
Add _MASK suffix to CM_FCLKEN_IVA2 bitfieds to conform with the rest
of the usage in cm-regbits-34xx.h of using _SHIFT and _MASK suffixes.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:48 -07:00
Kevin Hilman
24d82e3421 OMAP: omap_device: when 'called from invalid state', print state
The omap_device_[enable|idle|shutdown] functions print a warning
when called from an invalid state.  Print the invalid state in
the warning messages.  This also uses __func__ to get the function
name.

Also, move the entire print string onto a single line to facilitate
grepping or error messages.  Recent discussions on LKML show
strong preference for grep-able code vs. strict 80 column limit.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:45 -07:00
Kevin Hilman
0007122ad8 OMAP: omap_device: add omap_device_is_valid()
The omap_device struct contains a 'struct platform_device'.  Normally,
converting a platform_device pointer to an omap_device pointer
consists of simply doing a container_of(), as is done currently by the
to_omap_device() macro.

However, if this is attempted when using platform_device that has not
been created as part of the omap_device creation, the container_of()
will point to a memory location before the platform_device pointer
which will contain random data.

Therefore, we need a way to detect valid omap_device pointers.  This
patch solves this by using the simple magic number approach.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:45 -07:00
Tony Lindgren
80c20d543d Merge branch 'omap-fixes-for-linus' into omap-for-linus 2010-02-17 14:08:58 -08:00
Ranjith Lohithakshan
b72c7d5435 omap: Remove DEBUG_FS dependency for mux name checking
The check for a valid mux name should be performed regardless of whether
DEBUG_FS is enabled or not. Otherwise without DEBUG_FS, we get:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
last sysfs file:
Modules linked in:
CPU: 0    Not tainted  (2.6.33-rc8 #10)
PC is at strcmp+0x18/0x40
LR is at omap_mux_init_signal+0x68/0x14c
...

This fixes the issue currently seen with boards not booting up
if DEBUG_FS is not enabled in defconfig.

Note that the earlier ifndef + ifdef now becomes simpler ifdef else:
If CONFIG_OMAP_MUX is selected, we use pin names. If it's not selected,
we only want the GPIO to mux register mapping.

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-17 09:51:41 -08:00
Jorge Eduardo Candelaria
d6a2d9b800 OMAP4: MCPDM: Register McPDM platform device
Add platform device for McPDM interface in OMAP4 and register
its memory and irq resources.

Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Jorge Eduardo Candelaria
302720f3b7 ARM: OMAP4: Add McPDM base address
Define McPDM physical and L3 base address for OMAP4

Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Jorge Eduardo Candelaria
57852d761a OMAP4: IRQ: Add McPDM IRQ definition
Support for McPDM IRQs in OMAP4

Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Felipe Balbi
52abcbc9c4 arm: omap: kill compile warning on board-4430-sdp.c
sdp4430_uart_config isn't used anywhere, so remove it.

Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Vaibhav Hiremath
91fbb8c6d9 AM35xx: Update irq.h for AM35xx IPSS module interrupts
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Vaibhav Hiremath
07dcbd0786 AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit definition
AM3517/05 has few additional control module registers to control
the new IP's, like VPFE, USBOTG, CPGMAC.

This patch adds the bit defination for INTR_CLR and SW_RST control
register.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Vaibhav Hiremath
e3d4d0a238 AM35xx: Introduce am35xx.h file
Add base address definations for new AM35xx IPSS modules, like
VPFE, USBOTG, CPGMAC.

Please note that the OMAP34xx IVA2 memory space is being used for
AM35xx IPSS modules.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Lesly A M
a1e63642a9 omap3: pm: Add T2 Keypad as a wakeup source
Changes for setting the padconf value for sys_nirq line which is
connected to T2 INTR1. This will fix the T2 keypad wakeup.

Signed-off-by: Lesly A M <x0080970@ti.com>
Signed-off-by: Teerth Reddy <teerth@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Tony Lindgren
321cfc851d omap3: Clean-up for omap_mux_init
Get rid of the ifdeffery in omap_mux_init by creating
omap_mux_init_package and omap_mux_init_signals functions.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Adrian Hunter
b702b1060a omap_hsmmc: allow compile without regulator framework
It is still possible to use the omap_hsmmc module
without the regulator framework.  Accordingly, ifdef
out regulator-specific functions.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:35 -08:00
Adrian Hunter
e0eb242446 omap_hsmmc: Allow for a shared VccQ
EMMC can have two voltage supplies, Vcc and VccQ
which are implemented in the code as consumer
supplies vmmc and vmmc_aux.

If the regulator that supplies vmmc_aux is shared
with other consumers, then sending it to sleep
will disrupt those consumers.  However, the
TWL4030-family regulators may have OFF remapped
to SLEEP, in which case 'regulator_disable()'
will put the regulator to sleep only when all
consumers are disabled - which is the desired
behaviour.

This patch adds a platform data field to allow
that option.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:34 -08:00
Adrian Hunter
6da20c89af omap_hsmmc: Ensure regulator enable / disable are paired
Stop using 'regulator_is_enabled()' and just pair enables
with disables so that the regulator reference counts can
work correctly.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:34 -08:00
Adrian Hunter
4380eea266 omap_hsmmc: Fix disable timeouts
Disable timeouts are in msecs not jiffies.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:34 -08:00
Adrian Hunter
1df58db8a2 omap_hsmmc: Allow for power saving without going off
An eMMC may be always powered on, so that the lowest
power saving state possible is sleeping. Add a field
to the platform data to indicate that.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:34 -08:00
Adrian Hunter
ce6f00165d omap: RX51: Remux to pull eMMC lines down when powering off
It has been discovered that, when eMMC is powered off, current
will flow from OMAP eMMC data pull-ups to the eMMC voltage supply.
Configuring pads for OMAP off-mode does not help because eMMC is
powered off independently of OMAP off-mode.  Hence the pads are
now re-configured when eMMC is powered on or off.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 10:03:34 -08:00